关键词: 可测试性设计 追踪调试 故障测试 边界扫描

Abstract:

Commonly, testability design and debugging structure are made separately, which need a great deal of additional hardware resources. However, they are   all based on the scan technology, and their similar structures are a waste of hardware resources. Integrating the test logic with the debnging logic can  reduce the cost of design and verification, and save the manufacturing cost. In this paper, an integrated structure of the two tests is proposed. This   structure can supply high fault coverage near 100%, and a strong debugging ability of observing and setting any bit of internal registers through the JT  AG ports.

Key words: （testability design, debug, fault test, boundary scan）