关键词: FPGA组 ASIC验证 可配置原型 分割算法

Abstract:

With the rapid growth of the ASIC design size and complexity, traditional verification approaches can hardly meet the emerging requirements. A new ASI C verification approach based on FPGAs can shorten the development cycle efficiently, implement verification more quickly and completely and satisfy the  requirements of ASIC verification better. This paper discusses the reconfigurable interconnection structure of prototype systems, presents a partitioni ng algorithm, and gives the corresponding imolementation.

Key words: （multiple FPGAs;ASIC verification, reconfigurable prototype;partitioning algorithm）