[1]JEDEC DDR3 SDRAM specification [S]. JEDEC JESD793E, JEDEC Solid State Technology Association 20100701.
[2]Brennan C,Tudor C, Schroeter E, et al. Signal integrity and PCB layout considerations for DDR2800 Mbps and DDR3 memories[R]. Silicon Valley.CDNLive Silicon Valley, 2007.
[3]Mahajan R. Memory design consideration when migrating to DDR3 interface from DDR2[R]. MemCore Inc,2007.
[4]Chuang Haohsiang,Wu Shujung,Hong Mingzhang,et al. Power integrity chippackagePCB cosimulation for I/O interface of DDR3 highspeed memory[C]∥Proc of Electrical Design of Advanced Packaging and Systems Symposium,2008:3134.
[5]Ren Jihong,Oh Dan, Chang S, et al. Statistical link analysis of highspeed memory I/O interfaces during simultaneous switching events[C]∥Proc of IEEEEPEP Performance of Electronic Packaging, 2008:2528.
[6]Swaminathan M, Engin A E.Power integrity modeling and design for semiconductors and systems[M].New Jersey: Prentice Hall, 2008.
[7]Popovich M, Friedman E G. Decoupling capacitors for multivoltage power distribution systems[J]. IEEE Transactions on Very Large Scale Integration Systems, 2006,14(3):217228.
[8]Pitica R F D. Prelayout power integrity analysis in the design flow of a PCB[C]∥Proc of 2011 IEEE 17th International Symposium for Design and Technology in Electronic Packaging, 2011:7780.
[9]Shi Linseng. Cosimulation and codesign of DDR3 system based on creative CPU[D].Changsha:National University of Defense Technology, 2011. (in Chinese)
[10]Song Yonggao.System level high speed parallel busDDR3 codesign simulation and optimization [D].Changsha: National University of Defense Technology,2013. (in Chinese)
附中文参考文献:
[9]史林森. 基于自主CPU的DDR3系统协同仿真与设计[D].长沙:国防科学技术大学, 2011.
[10]宋永篙. 系统级高速并行总线—DDR3协同设计与仿真优化[D].长沙:国防科学技术大学,2013. |