[1]Gupta A, Kim Y, Urgaonkar B. DFTL:A flash translation layer employing demandbased selective caching of pagelevel address mappings[C]∥Proc of ASPLOS, 2009:229240.
[2]You Byoungsung,Park Jinsu,Lee Sangdon,et al. A high performance codesign of 26 nm 64 Gb MLC NAND flash memory using the dedicated NAND flash controller[J]. Journal of Semiconductor Technology and Science, 2011, 11(2):121129.
[3]Goldman M, Pangal K, Naso G, et al. 25nm 64Gb 130mm2 3bpc NAND flash memory[C]∥Proc of the 3rd IEEE International Memory Workshop, 2011:14.
[4]Grupp L M, Davis J D, Swanson S. The bleak future of NAND flash memory[C]∥Proc of FAST’12,2012:2.
[5]Im S, Shin D. Flashaware RAID techniques for dependable and highperformance flash memory SSD[J]. IEEE Transactions on Computers, 2011, 60(1):8092.
[6]Lee Y, Jung S, Song Y Ho. FRA:A flashaware redundancy array of flash storage devices[C]∥Proc of CODES+ISSS’09, 2009:163172.
[7]Du Yimo, Xiao Nong, Liu Fang, et al. MuLeRAID:Constructing large scale and highperformance SSD with multiple level RAID architecture[J]. Journal of Computer Research and Development, 2012,49(z1):111117.(in Chinese)
[8]Narayanan D,Thereska E,Donnelly A,et al.Migrating server storage to SSDs:Analysis of tradeoffs[C]∥Proc of EuroSys’09, 2009:145158.
[9]Laboratory for Advanced System Software. UMass Trace Repository[EB/OL].[20091016].http://www.traces.cs.umass.edu/.
附中文参考文献:
[7]杜溢墨,肖侬,刘芳,等. MuLeRAID:面向大容量高性能SSD的层次化RAID[J].计算机研究与发展,2012,49(z1):111117. |