基于TIA/EIA-899标准的TYPE-I型M-LVDS接收器设计

J4 ›› 2015, Vol. 37 ›› Issue (03): 452-456.

基于TIA/EIA-899标准的TYPE-I型M-LVDS接收器设计

李智1,2，陈迪平1，赵建中2，曹成成1,2

（1.湖南大学物理与微电子科学学院，湖南长沙 410082；2.中国科学院微电子研究所，北京 100029）

收稿日期:2014-01-07 修回日期:2014-03-17 出版日期:2015-03-25 发布日期:2015-03-25
基金资助:
湖南省工业支撑项目（2013GK3019）

Design of a TYPE-I M-LVDS receiver IC
based on TIA/EIA-899 standard

LI Zhi1,2，CHEN Diping1，ZHAO Jianzhong2，Cao Chengcheng1,2

（1.School of Physics and Electronics,Hunan University,Changsha 410082;
2.Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China）

Received:2014-01-07 Revised:2014-03-17 Online:2015-03-25 Published:2015-03-25

摘要/Abstract

摘要：

提出了一种基于TIA/EIA-899标准的TYPE-I型M-LVDS接收芯片的实现方案，设计了一种新颖的共模搬移电路在实现超越电源电压轨的共模输入范围的同时简化了后级电路设计，节约了面积和功耗，电路中预放大器将输入信号放大一定倍数，迟滞比较器为系统引入迟滞效果。芯片采用GSMC 0.18 μm 1P6M CMOS工艺流片验证。测试结果表明，该芯片共模输入范围为-1.4 V~3.8 V，信号传输速率大于250 Mbps，具有典型值为28 mV的迟滞效果。关键词：

关键词: M-LVDS, 高速接口, 共模电压, 迟滞

Abstract:

We propose an implementation scheme for a TYPE-I M-LVDS receiver based on TIA/EIA-899 standard.A novel common-mode voltage shift circuit is designed to realize an input common-mode range that is beyond the rail of the power voltage,which can simplify the post stage circuit,thus saving area and power consumption.The pre-amplifier in the receiver can provide a fixed magnification for input signals,and the hysteresis comparator brings hysteresis effect to the system.The chip is fabricated in GSMC 0.18 μm 1P6M CMOS technology,and the test results indicate that the receiver has an input commonmod range of -1.4 V~3.8 V,a signaling rate greater than 250 Mbps,and a typical hysteresis voltage is 28 mV.

Key words: M-LVDS;high-speed interface;common-mode voltage;hysteresis

李智1,2，陈迪平1，赵建中2，曹成成1,2. 基于TIA/EIA-899标准的TYPE-I型M-LVDS接收器设计[J]. J4, 2015, 37(03): 452-456.

LI Zhi1,2，CHEN Diping1，ZHAO Jianzhong2，Cao Chengcheng1,2. Design of a TYPE-I M-LVDS receiver IC
based on TIA/EIA-899 standard [J]. J4, 2015, 37(03): 452-456.