• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学

• 高性能计算 • 上一篇    下一篇

基于FPGA的HS400模式eMMC控制器设计与实现

张煜1,2,陈微1,吴利舟1,2,肖侬1,2   

  1. (1.国防科技大学计算机学院,湖南 长沙 410073;
     2.国防科技大学高性能国家重点实验室,湖南 长沙 410073)
  • 收稿日期:2017-01-10 修回日期:2017-03-30 出版日期:2018-06-25 发布日期:2018-06-25
  • 基金资助:

    国家自然科学基金(61433019,61232003)

Design and implement of an eMMC
controller in HS400 mode based on FPGA

ZHANG  Yu1,2,CHEN Wei1,WU Lizhou1,2,XIAO Nong1,2   

  1. (1.College of Computer,National University of Defense Technology,Changsha 410073;
    2.State Key Laboratory of High Performance Computing,National University of Defense Technology,Changsha 410073,China)
     
  • Received:2017-01-10 Revised:2017-03-30 Online:2018-06-25 Published:2018-06-25

摘要:

介绍了eMMC及其在HS400高速数据传输模式下的工作原理,提出了一种eMMC控制器的设计方案。实现了200 MHz工作频率下,使用DDR传输模式进行数据传输的eMMC控制器,并通过CRC校验模块实现对传输数据的CRC校验,增强了系统的可靠性。实验平台采用母板/子板总体架构,在Xilinx Zynq7000 FPGA开发板Zedboard上实现eMMC控制器,通过FMC接口与eMMC芯片子板进行通信传输。仿真及板级测试表明, HS400模式下数据读写
的传输速率最高可达400 MB/s,能够在实际的eMMC开发中有效提高eMMC设备的访问性能。
 
 

关键词: eMMC, HS400模式, 控制器, FPGA

Abstract:

We introduce the working principle of eMMC chip and its HS400 high speed data transmission mode, the design scheme of an eMMC controller, and the result of hardware verification. An eMMC controller that uses the DDR transmission mode for data transmission is implemented at a working frequency of 200 MHz, and the CRC verification module is employed to achieve the transmission data CRC checksum to enhance system reliability. The experimental platform adopts the motherboard/subboard architecture, and the eMMC controller is ultimately implemented on the Xilinx Zynq7000 FPGA Zedboard development board to realize communication through the FMC interface and eMMC chip board. Simulation and boardlevel tests show that data read and write operations in the HS400 mode can achieve a data transfer rate of up to 400 MB/s, which can effectively improve the access performance of the device during the actual eMMC development.
 

Key words: eMMC, HS400 mode, controller, FPGA