关键词: 动态可重构；高效视频编码；率失真优化；阵列处理器 ,

Abstract: In the implementation based on video array processor, the flexible coding blocks of High Efficiency Video Coding (HEVC) increase the difficulty of hardware implementation of the rate- distortion optimization algorithm, and it is difficult to realize the array size and flexible switching of different blocks. Aiming at this problem, a dynamic reconfigurable implementation method of rate- distortion optimization is proposed. The dynamic reconfiguration mechanism based on context switching completes the flexible switching among algorithms of different sizes and different block sizes, and uses the rate-distortion optimization algorithm as the basis of discriminating the intra-mode selection to realize the intra-prediction mode reconfiguration. Experimental results show that, compared with the rate- distortion optimization algorithm implemented by dedicated hardware, when the algorithm is flexibly switched, the hardware area is reduced by 8.2%, and the number of clock cycles of algorithm execution is reduced by 165%.

Key words: dynamically reconfigurable, high efficiency video coding, rate distortion optimization, array processor