• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学 ›› 2024, Vol. 46 ›› Issue (04): 599-605.

• 高性能计算 • 上一篇    下一篇

面向芯粒间互连的低功耗发射机驱动设计

任博琳,肖立权,齐星云,张庚,王强,罗章,庞征斌,徐佳庆   

  1. (国防科技大学计算机学院,湖南 长沙 410073)

  • 收稿日期:2023-09-12 修回日期:2023-11-19 接受日期:2024-04-25 出版日期:2024-04-25 发布日期:2024-04-17
  • 基金资助:
    国家重点研发计划(2022YFB4401504)

A low-power transmitter driver for die to die

REN Bo-lin,XIAO Li-quan,QI Xing-yun,ZHANG Geng,WANG Qiang,LUO Zhang,PANG Zheng-bin,XU Jia-qing   

  1. (College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)
  • Received:2023-09-12 Revised:2023-11-19 Accepted:2024-04-25 Online:2024-04-25 Published:2024-04-17

摘要: 面向UCIe协议提出的芯粒间互连标准,设计与实验了一种面向芯粒(Chiplet)间互连的低功耗发射机驱动。该驱动电路采用了SST电压模驱动器,功耗仅为CML电流模驱动器结构的1/4。此外,该驱动电路基于可调前馈均衡技术,针对不同的信道衰减调整均衡强度,采用去加重均衡的方式提高发射信号质量,最终降低码间干扰。本文设计采用CMOS 28 nm工艺设计,前端仿真结果表明,在0.9 V电压供电时,最大均衡强度为-3.7 dB,当32 Gbps的NRZ信号通过21 mm的信道时(16 GHz奈奎斯特频率处衰减为-2.37 dB),选择合适均衡强度后,输出波形眼图眼高为253 mV(71.8%),眼宽为27 ps(87%),仿真功耗仅为4.0 mW。

关键词: 芯粒, 前馈均衡器, SST驱动器, 高速接口电路, 发射机

Abstract: A low-power transmitter driver for chiplet interconnection was designed and experimentally implemented based on the inter-chip interconnection standard proposed by the UCIe protocol. The driver circuit adopts a source series terminated (SST) driver, whose power consumption is only 1/4 that of the current mode logic (CML) structure. In addition, based on adjustable feedforward equalization technology, the driver circuit adjusts the equalization strength for different channel attenuations. By de-emphasizing equalization, it enhances the quality of the transmitted signal, ultimately reducing inter-symbol interference. This circuit was designed under CMOS 28 nm process. The front-end simulation results show that the maximum equalization intensity is -3.7 dB when the 0.9 V voltage is supplied. When the 32 Gbps NRZ signal passes through the 21 mm channel (the attenuation at the 16 GHz Nyquist frequency is -2.37 dB), after adjusting the appropriate equalization intensity, the eye height of the output waveform eye diagram is 253 mV (71.8%), the eye width is 27 ps (87%), and the simulation power consumption is only 4.0 mW.

Key words: Chiplet, feedforward equalizer(FFE), source series terminated(SST) driver, serDes, transmitter