• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学 ›› 2024, Vol. 46 ›› Issue (08): 1390-1394.

• 高性能计算 • 上一篇    下一篇

基于BOOM处理器的访存逻辑优化

周蔺宁,刘杰,李洪奎,付浩东,刘红海,肖浩   

  1. (湖州师范学院信息工程学院,浙江 湖州 313000)
  • 收稿日期:2023-11-14 修回日期:2023-12-29 接受日期:2024-08-25 出版日期:2024-08-25 发布日期:2024-09-02
  • 基金资助:
    湖州市公益重点项目(2019GZ10);浙江省重点实验室项目(2020E10017)

Optimization of memory access logic in BOOM processor

ZHOU Lin-ning,LIU Jie,LI Hong-kui,FU Hao-dong,LIU Hong-hai,XIAO Hao   

  1. (School of Information Engineering,Huzhou University,Huzhou 313000,China)
  • Received:2023-11-14 Revised:2023-12-29 Accepted:2024-08-25 Online:2024-08-25 Published:2024-09-02

摘要: BOOM处理器采用的Store指令回查策略虽然解决了访存指令乱序执行引发的数据冲突问题,但是该策略会导致流水线的大量冲刷,降低了处理器的性能。对此,提出了一种访存指令的相关性预测方法。该方法取消了Load指令访存前的查询操作,增加了Load指令相关性预测表,只有预测为无相关性的Load指令才可以乱序执行。这种方法在保证程序逻辑正确的前提下避免了大量冲刷流水线。测试程序采用SPEC CPU 2006下的7个子程序,实验结果表明,改进后的处理器执行程序的性能平均提升了3.5%。

关键词: 乱序执行, 访存指令, 相关性预测

Abstract: Although the Store instruction backtracking strategy adopted by BOOM processors solves the problem of data conflicts caused by out-of-order execution of memory access instructions, this strategy can lead to a large amount of pipeline flushing and reduce the processor performance. To address this, a correlation prediction method for memory access instructions is proposed. This method cancels the query operation before the Load instruction accesses memory and adds a Load instruction correlation prediction table. Only Load instructions that are predicted to be uncorrelated can be executed in disorder. This method avoids a large amount of pipeline flushing while ensuring the correctness of program logic. The test program uses 7 subroutines under SPEC CPU 2006, and the experimental results show that the improved processor's execution performance is improved by 3.5% on average.

Key words: out-of-order execution, memory access instruction, correlation prediction