• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学 ›› 2025, Vol. 47 ›› Issue (9): 1521-1534.

• 高性能计算 • 上一篇    下一篇

芯粒互联接口中多协议支持技术及标准化研究

何星洋1,2,周宏伟1,2,周雨萱1,2,孙玉波3,黎梦金1,2   

  1. (1.国防科技大学计算机学院,湖南 长沙 410073;2.国防科技大学先进微处理器芯片与系统重点实验室,湖南 长沙 410073;  3.长沙理工大学计算机与通信工程学院,湖南 长沙 410114)

  • 收稿日期:2024-11-02 修回日期:2024-12-04 出版日期:2025-09-25 发布日期:2025-09-22
  • 基金资助:
    湖南省教育厅项目(XJCX2023169)

Research on multi-protocol support technology and standardization in Chiplet interconnection interface

HE Xingyang1,2,ZHOU Hongwei1,2,ZHOU Yuxuan1,2,SUN Yubo3,LI Mengjin1,2   

  1. (1.College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;
    2.Key Laboratory of Advanced Microprocessor Chips and Systems,
    National University of Defense Technology,Changsha 410073;
    3.School of Computer Science and Technology,Changsha University of Science and Technology,Changsha 410114,China)
  • Received:2024-11-02 Revised:2024-12-04 Online:2025-09-25 Published:2025-09-22

摘要: 通过芯粒集成构建更大规模的芯片成为后摩尔时代突破芯片工艺墙、存储墙、功耗墙和扩展性墙的有效手段。 制定芯粒互联接口规范是实现异构芯粒集成的前提,对于简化芯粒适配、提高芯粒和芯粒互联接口复用和加速多芯粒SoC芯片设计具有重要意义。 由于不同类型的芯粒在协议层采用不同的协议标准,芯粒互联接口需要支持多个协议。 为此,提出一种按大类支持的多协议支持技术,将协议根据其报文特点分为两类,一类为符合固定模式特点的协议,另一类为符合流模式特点的协议。该技术可以直接支持符合这两类报文特点的协议,对不符合这两类的报文类型则通过“原生模式”间接支持。该技术还支持任意两个协议并发并且可以更高效地支持CXL和UCIe。该技术通过微包级兼容技术提高了对各种协议间接支持的效率,通过把链路管理信息在数据负载中的填充交由协议层负责实现了协议层与适配器层彻底解耦。 在此基础上,设计了支持PCIe和CXL.mc协议并发执行的芯粒互联接口,搭建了仿真验证环境。 实验结果表明了所提技术支持多个协议和支持多协议并发的可行性和正确性。

关键词: 芯粒集成, 芯粒互联规范, 芯粒互联接口, 多协议支持技术, 协议并发

Abstract: Chiplet integration has emerged as an effective approach to overcoming the limitations of chip fabrication, memory bandwidth, power consumption, and scalability in the post-Moore era. Establishing standardized Chiplet interconnection interfaces is a prerequisite for heterogeneous Chiplet integration, significantly simplifying Chiplet adaptation, improving the reusability of Chiplets and interconnect interfaces, and accelerating multi-Chiplet SoC design. Since different types of Chiplets adopt varying protocol standards at the protocol layer, Chiplet interconnection interface must support multiple protocols. To address this, we propose a multi-protocol support technology based on broad categorization, dividing protocols into two classes according to their packet characteristics: fixed-pattern protocols and stream-pattern protocols. This technology directly supports protocols conforming to these two categories, while indirectly supporting non-conforming packet types through a “native mode”. Additionally, it enables concurrent execution of any two protocols and provides enhanced support for CXL and UCIe. The technology improves indirect protocol support efficiency via micro-packet-level compatibility and achieves complete decoupling between the protocol and adapter layers by delegating link management information embedding in data payloads to the protocol layer. Based on this, we designed a Chiplet interconnection interface supporting concurrent PCIe and CXL.mc protocols and established a simulation verification environment. Experimental results confirm the feasibility and correctness of the proposed technology in multi-protocol support and concurrent protocol execution.

Key words: Chiplet integration, Chiplet interconnect specification, Chiplet interconnection interface, multi-protocol support technology, multi-protocol concurrency