大规模QR分解在信号处理、图像处理、计算结构力学等领域有着广泛的应用。大规模矩阵QR分解主要在高性能并行机上进行运算，目前还没有基于FPGA平台的加速实现。本文在分析快速Givens Rotation QR分解算法特征的基础上，提出并实现了一种细粒度并行QR分解算法，并在Altera StratixII FPGA平台上实现可扩展QR分解线性阵列处理器。相对于单处理单元，该阵列处理器可取得近似线性加速比，显示了良好的可扩展性。在100MHz频率下的性能测试结果表明，相对于2.0GHz的Pentium双核通用微处理器，该阵列处理器可取得19倍的加速比。

Largescale QR decomposition is widely used in many fields,such as signal processing,large image processing,and computational structure dynamics,and so on. Traditional methods adopt  parallel computers to accelerate  largescale QR decomposition,which is a computationintensive algorithm. This paper presents a finegrained parallel implementation of Givens Rotation QR decomposition on FPGA. A scalable linear array of processing elements (PEs),which is the core component of our hardware design,is proposed to implement this algorithm. To our knowledge,this is the first  FPGAbased implementation of largescale QR decomposition. A total of 15 GRPEs can be integrated into an Altera StratixII EP2S130F1020C5 FPGA.The experimental results show that a speedup up to 19 can be achieved relative to the Pentium Dual CPU.