• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊
论文

2~5GHz 0.18μm CMOS宽带低噪声放大器设计

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  • (并行与分布处理国防科技重点实验室,湖南 长沙 410073)
何小威(1980),男,湖北宜城人,博士生,研究方向为模拟和射频集成电路设计。张民选(1954),男,教授,博士生导师,研究方向为高性能计算机系统结构、微处理器设计及ASIC技术等。

收稿日期: 2009-10-05

  修回日期: 2009-12-08

  网络出版日期: 2010-02-25

基金资助

国家自然科学基金资助项目(60873212)

Design of a 2~5GHz 0.18μm CMOS  Wideband Low Noise Amplifier

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  • (National Laboratory for Parallel and Distributed Processing,Changsha  410073,China)

Received date: 2009-10-05

  Revised date: 2009-12-08

  Online published: 2010-02-25

摘要

本文设计实现了一个2~5GHz的两级CMOS低噪声放大器(LNA),可应用在超宽带的下半频段(3.1~5GHz)。LNA由两级组成,第一级是一个共栅级,保持良好的线性度并完成较好的输入匹配;第二级是一个共源级堆叠一个电流源,在保持低噪声系数的同时降低功耗。通过级联共栅和共源结构进行增益补偿,所设计的LNA具有近似恒定的增益和噪声系数。采用0.18μm CMOS工艺实现后,模拟结果表明,增益和噪声系数在2~5GHz频率范围内分别为11.5dB和5.1dB,输入反射系数低于-22dB。在4GHz时,模拟得到的三阶交调点为-10dBm。在1.8V电源电压下,LNA的功耗约为11mW。

本文引用格式

何小威,张民选 . 2~5GHz 0.18μm CMOS宽带低噪声放大器设计[J]. 计算机工程与科学, 2011 , 33(2) : 61 -64 . DOI: 10.3969/j.issn.1007130X.2011.

Abstract

A twostage 25GHz CMOS Low Noise Amplifier(LNA) for the lower side of UltraWideBand(UWB) applications(3.15GHz) is presented. This LNA consists of two stages. The first stage is a commongate structure maintaining good linearity with better input matching; the second stage is a commonsource stage stacked with a current mirror, which obtains low Noise Figure(NF) and reduces the LNA’s power consumption. By introducing commongate and commonsource stages to compensate gain mutually, the proposed LNA has achieved nearly flat power gain and NF. This LNA has been implemented by a 0.18μm CMOS process. The successive simulation results indicate that the power gain(S21) keeps 11.5dB over the wide frequency band of 25GHz with NF 5.1dB and input return loss(S11) below 22dB in the entire band. The simulated inputreferred thirdorder intercept point(IIP3) at 4GHz is 10dBm. The LNA consumes about 11mW under the 1.8V supply.

参考文献

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