模板操作在GPU上的实现与优化
收稿日期: 2009-07-26
修回日期: 2009-10-21
网络出版日期: 2011-03-25
基金资助
国家自然科学基金资助项目（60621003）
Implementation and Optimization of Stencil Applications on GPUs
Received date: 2009-07-26
Revised date: 2009-10-21
Online published: 2011-03-25
随着GPU的快速发展，使用GPU来加速科学计算应用已成为必然趋势。本文抽取了SPEC2000中富含模板操作的Mgrid的两个典型子程序Rprj3和Interp，使用Brook+语言把它们移植到AMD GPU上运行。采用Brook+语言提供的线程调节机制，我们实现了不同线程粒度下的程序版本，并分析了加速比不同的原因，总结了线程粒度调节对模板程序移植的指导意义。我们使用AMD Radeon HD4870 GPU作为实验平台，对比Intel Xeon E5405 CPU上的运行结果发现，在最大规模下，Rprj3获得的相对于CPU版本的加速比为5.37×, Interp获得的相对于CPU版本的加速比为12.8×。
方旭东,唐玉华,王桂彬,唐滔 . 模板操作在GPU上的实现与优化[J]. 计算机工程与科学, 2011 , 33(3) : 41 -45 . DOI: 10.3969/j.issn.1007130X.2011.
With the fast development of GPUs, using them to accelerate scientific computing applications is becoming an inevitable trend. In this paper, we port two typical subroutines Rprj3 and Interp from Mgrid which contains rich stencil operations in SPEC2000 to run on an AMD GPU using Brook+. Using a thread granularity tuning mechanism provided by Brook+, we implement different ported program versions and analyze their performances. We also conclude how to utilize thread granularity tuning to optimize stencil program transplantation. Our experimental results show that under the largest problem size, Rprj3 obtains a speedup of 5.37 over its CPU version while Interp gains a speedup of 12.8 over its CPU version.
Key words： GPU;optimization;stencil
［1］AMD.ATI Stream Computing User Guide v1.4 Beta［EB/OL］.［20090705］. http://developer.amd.com/gpu_assets/Stream_Computing_User_Guide.pdf.
［2］NVIDIA.Compute Unified Device Architecture Programming Guide v2.1 Beta［EB/OL］.［20090625］. http://developer.download.nvidia. com/compute/cuda/1_0/NVIDIA_CUDA_Programming_Guide_1.0.pdf.
［3］Ryoo S, Rodrigues C I, Baghsorkhi S S,et al. Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA［C］∥Proc of the ACM SIGPLAN Symp on Principles and Practice of Parallel Programming,2008:7382.
［4］Datta K, Murphy M, Volkov V,et al. Stencil Computation Optimization and AutoTuning on StateoftheArt Multicore Architectures［C］∥Proc of the 2008 ACM/IEEE Conf on Supercomputing,2008:1521.
［5］Fan Z, Qiu F, Kaufman A,et al. GPU Cluster for High Performance Computing［C］∥Proc of the 2004 ACM/IEEE Conf on Supercomputing,2004:4753.
［6］Buck I. Brook Specification V0.2［EB/OL］.［20090708］. http://hci.stanford.edu/cstr/reports/200304.pdf.
［7］Ryoo S, Rodrigues C I, Stone S S, et al.Program Optimization Carving for GPU Computing［J］. Journal of Parallel Distributed Computing, 2008,68(10):13891401.
［8］Ryoo S, Rodrigues C I, Baghsorkhi S S, et al. Optimization Principles and Application Performance Evaluation of a Multithreaded GPU Using CUDA［C］∥Proc of the ACM SIGPLAN Symp on Principles and Practice of Parallel Programming,2008:7382.
［9］Jang B, Do S, Pien H. ArchitectureAware Optimization Targeting Multithreaded Stream Computing［C］∥Proc of the Second Workshop on GeneralPurpose Compution on Graphics Processing Units,2009:6270.
［10］Wang G, Yang X J, Zhang Y, et al. Program Optimization of Stencil Based Application on the GPUAccelerated System［C］∥Proc of the Int’l Symp on Parallel and Distributed Processing and Applications,2009:219225.
［11］Li Z,Song Y. Automatic Tiling of Iterative Stencil Loops［J］. ACM Transactions on Programming Languages and Systems,2004,26(6):9751028.
［12］Krishnamoorthy S,Baskaran M M, Bondhugula U, et al. Effective Automatic Parallelization of Stencil Computations［J］.SIGPLAN Notices,2007,42(6):235244.
/
| 〈 |
|
〉 |