深度驱动图划分的关键路径延时优化研究

余学雯, 陈海燕, 黄鹏程

doi:10.3969/j.issn.1007-130X.2026.04.003

计算机工程与科学 >

2026 , Vol. 48 >Issue 4: 590 - 598

DOI: https://doi.org/10.3969/j.issn.1007-130X.2026.04.003

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深度驱动图划分的关键路径延时优化研究

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(1.先进微处理器芯片与系统重点实验室，湖南长沙 410073；
2.国防科技大学计算机学院，湖南长沙 410073)

收稿日期: 2024-09-09

修回日期: 2025-01-16

网络出版日期: 2026-04-29

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Depth-driven graph partitioning for critical path delay optimization

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(1.Key Laboratory of Advanced Microprocessor Chips and Systems，Changsha 410073;
2.College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)

Received date: 2024-09-09

Revised date: 2025-01-16

Online published: 2026-04-29

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摘要

在微处理器设计中，关键路径延时是制约微处理器主频和性能提升的重要因素，而日益增长的设计复杂度使传统优化方法面临着挑战。针对这一难题，提出了一种自动化的深度驱动图划分的关键路径延时优化策略，并实现了相应算法。将延时优化问题建模为有向无环图划分选择问题，基于半定制设计流程所得的逻辑网表，利用深度驱动图划分识别并选取一批具有优化潜力的子电路结构，进行逻辑重构，并替换逻辑网表中相应的逻辑单元集。实验结果表明，提出的算法可对电子设计自动化工具设计完成的电路进行优化，有效降低了关键路径上的逻辑深度，进而为在有限成本下优化关键路径延时提供了一种有效的策略，以实现微处理器性能的提升。

关键词： 关键路径; 延时优化; 逻辑深度; 图划分; 逻辑重构

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余学雯, 陈海燕, 黄鹏程 . 深度驱动图划分的关键路径延时优化研究[J]. 计算机工程与科学, 2026 , 48(4) : 590 -598 . DOI: 10.3969/j.issn.1007-130X.2026.04.003

Abstract

In microprocessor design, critical path delay is a crucial factor that restricts the increase in the microprocessor's clock frequency and performance enhancement. The ever-increasing design complexity poses challenges to traditional optimization methods. To address this difficult issue, an automated critical path delay optimization strategy based on depth-driven graph partitioning is proposed, along with the implementation of the corresponding algorithm. The delay optimization problem is modeled as a directed acyclic graph (DAG) partitioning and selection problem. Leveraging the logic netlist designed in the semi-custom design flow, the strategy utilizes depth-driven graph partitioning to identify and select a set of sub-circuit structures with optimization potential. These sub-circuits then undergo logical reconstruction, and the corresponding logic cells in the logic netlist are replaced accordingly. Experimental results demonstrate that the proposed algorithm can optimize circuits designed by electronic design automation (EDA) tools, effectively reducing the logical depth along critical paths. Consequently, it provides an effective strategy for optimizing critical path delay within limited costs, thus aiming to achieve an improvement in microprocessor performance.

Key words： critical path; delay optimization; logic depth; graph partitioning; logic restructuring

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