• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊
高性能计算

基于 28 nm CMOS工艺采用亚阈值区MOSFET的低温漂系数高电源抑制电流模带隙基准

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  • (国防科技大学计算机学院,湖南 长沙  410073)

收稿日期: 2024-10-18

  修回日期: 2025-03-20

  网络出版日期: 2026-05-21

基金资助

国家重点研发计划(2022YFB2803101)


A current-mode bandgap voltage reference with low temperature  coefficient  and high PSRR using subthreshold MOSFET in 28 nm CMOS

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  • (College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)

Received date: 2024-10-18

  Revised date: 2025-03-20

  Online published: 2026-05-21

摘要

随着集成电路核心器件尺寸缩小,大尺寸工艺逐渐不能满足先进技术条件下电路的指标要求。作为模拟电路中的基本单元,带隙电压基准需要适应工艺变化。采用28 nm CMOS工艺,提出一种在高带宽范围内具有良好电源抑制比的低温漂系数的带隙电压基准。与以往电路采用三极管产生正负温度系数电压不同,该带隙基准采用处于亚阈值区MOSFET的电压的温度特性产生基准电压,亚阈值区器件开启电压低,极大地降低了放大器的共模电压,增大了纵向电压裕度,通过增加电流镜结构产生二级电源与共栅管增大输出电阻来提高高带宽范围内的电源抑制比。该电压基准电路以电流模带隙基准为基础,采用1.8 V电源供电,tt工艺角下,在-40~125 ℃范围内提供943 mV的稳定基准电压,产生的基准电压温度系数为6.1 ppm/℃;在输入电压为1.5~5 V范围内,线性调整率为0.33%;电源抑制比在DC时为-64.3 dB,在0~16 kHz频率范围内具有低于-64.1 dB的电源抑制比,100 kHz时仍有-58 dB的电源抑制比;版图面积为0.003 8 mm2;工作时静态功耗为16.56 μW。

本文引用格式

赵成卓, 吕方旭, 徐炜遐, 黄恒, 罗章, 辛可为, 王文晨, 李萌, 赖明澈, 庞征斌 . 基于 28 nm CMOS工艺采用亚阈值区MOSFET的低温漂系数高电源抑制电流模带隙基准[J]. 计算机工程与科学, 2026 , 48(5) : 770 -778 . DOI: 10.3969/j.issn.1007-130X.2026.05.002

Abstract

As the size of core devices in integrated circuits shrinks, large-scale process gradually fails to meet the performance requirements of circuits under advanced technologies. As a fundamental unit in analog circuits, the bandgap voltage reference needs to adapt to process variations. This paper, utilizing a 28 nm CMOS process, proposes a current-mode bandgap voltage reference with excellent power supply rejection ratio (PSRR) over a wide bandwidth range and a low temperature coefficient. Unlike conventional circuits that employ bipolar transistors to generate positive and negative temperature coefficient voltages, this bandgap voltage reference generates a reference voltage by leveraging the temperature characteristics of MOSFET voltages in the subthreshold region. Subthreshold devices have a low turn-on voltage, significantly reducing the common-mode voltage of the amplifier, increasing the vertical voltage margin. By incorporating a current mirror structure to generate a secondary power supply and using a common-gate transistor to increase output resistance, the PSRR over a high bandwidth range is enhanced. Based on a current-mode bandgap reference, this voltage reference circuit operates with a 1.8 V power supply. Under the tt process corner, it provides a stable reference voltage of 943 mV within the temperature range of -40~125 ℃, with a temperature coefficient of the reference voltage of 6.1 ppm/℃. Within an input voltage range of 1.5~5 V, the line regulation is 0.33%. The PSRR is -64.3 dB at DC and remains below -64.1 dB within the frequency range of 0~16 kHz, still reaching -58 dB at 100 kHz. The layout area is 0.003 8 mm2, and the quiescent power consumption during operation is 16.56 μW.

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