赵成卓, 吕方旭, 徐炜遐, 黄恒, 罗章, 辛可为, 王文晨, 李萌, 赖明澈, 庞征斌
. 基于 28 nm CMOS工艺采用亚阈值区MOSFET的低温漂系数高电源抑制电流模带隙基准[J]. 计算机工程与科学, 2026
, 48(5)
: 770
-778
.
DOI: 10.3969/j.issn.1007-130X.2026.05.002
As the size of core devices in integrated circuits shrinks, large-scale process gradually fails to meet the performance requirements of circuits under advanced technologies. As a fundamental unit in analog circuits, the bandgap voltage reference needs to adapt to process variations. This paper, utilizing a 28 nm CMOS process, proposes a current-mode bandgap voltage reference with excellent power supply rejection ratio (PSRR) over a wide bandwidth range and a low temperature coefficient. Unlike conventional circuits that employ bipolar transistors to generate positive and negative temperature coefficient voltages, this bandgap voltage reference generates a reference voltage by leveraging the temperature characteristics of MOSFET voltages in the subthreshold region. Subthreshold devices have a low turn-on voltage, significantly reducing the common-mode voltage of the amplifier, increasing the vertical voltage margin. By incorporating a current mirror structure to generate a secondary power supply and using a common-gate transistor to increase output resistance, the PSRR over a high bandwidth range is enhanced. Based on a current-mode bandgap reference, this voltage reference circuit operates with a 1.8 V power supply. Under the tt process corner, it provides a stable reference voltage of 943 mV within the temperature range of -40~125 ℃, with a temperature coefficient of the reference voltage of 6.1 ppm/℃. Within an input voltage range of 1.5~5 V, the line regulation is 0.33%. The PSRR is -64.3 dB at DC and remains below -64.1 dB within the frequency range of 0~16 kHz, still reaching -58 dB at 100 kHz. The layout area is 0.003 8 mm2, and the quiescent power consumption during operation is 16.56 μW.