Abstract:

To meet the needs of a wide frequency range of digital systems, we design a wide output range, low phase jitter eightphase lock loop in the 0.13μm process. We first optimize the loop bandwidth through mathematical modeling to reduce the loop noise at the system level. A feedforward transfer tube unit is introduced to increase the oscillation frequency and to reduce the oscillator's phase noise. Finally, we leverage the D flipflop, which has a pseudostatic structure, to reduce the power consumption of phase detectors and dividers, and maximize the noise immunity. Simulation results show that the phase noise is -95 dBc/Hz@1 MHz,FOM power is 4.5 PJ@2 GHz when the VCO output frequency is 1.2 GHz.

Key words: CPPLL;loop bandwidth;low phase noise;multiphase;wide output range