关键词: 大规模集成电路 物理设计 布局规划 时序驱动

Abstract:

This paper proposes a timing-driven floorplan method based on groups in the physical design. This method employs available EDA tools and partitions the netlist into groups, and then utilizes the architecture experience of designers to layout, adjust and optimize the netlist. This method can backarmota te the better custom wire load model to the synthesis and improve the consistency between the synthesis and layout. This method can also distribute the  power and ground network based on groups and make it easy to route successfully. The experimental results on a 32 bits microprocessor, which has been ta  pouted successfully, show that the method can improve the timing of critical paths and accelerate the process of physical design

Key words: （VLSI, physical design, floorplan, timing-driven）