关键词: 磁盘阵列 现场可编程门阵列 奇偶校验

Abstract:

This paper deals with the hardware design of a RAID XOR processing engine based on the EP1C12Q240C8 FPGA IC chip of the Altera Cyclone series.This des  ign adopts the conception of parallelism.In order to provide the best performance,the parity check process is overlapped with the data transmission on t  he PCI bus,so the time spent on the whole task is equal to that of the data transmission on the PCI bus.Through software simulation and hardware impleme ntation,the results indicate that the designed circuit is reliable.

Key words: （RAID,FPGA,parity check）
（RAID,FPGA,parity check）