关键词: UML-RT序列图 系统芯片 事务 验证

Abstract:

An important problem faced by transaction-based systemon-chip verification is how to design the complex transaction test sequence.Scenario-based sequence diagram is a good way to capture the system-level functional specification.In the paper,we propose a method to support the transaction-level verification of SoC based on the UML-RT sequence diagrams.We use the UML-RT sequence diagram to capture the communication and collaboration behaviours among IPcores in SoC and build a high-level specification for transaction-level verification.Then these sequence diagrams will be used to guide the generation of transaction test sequences.We develop a component-based transaction verification environment named SoC-CBTVE.In SoC-CBTVE,using the method,we verify  a typical SoC design.Experimental results show that the UML-RT sequence diagram can capture the complex communication behaviours among IP cores in SoC design,and efficiently supports the SoC system-level functional verification.

Key words: UML-RT sequence diagram;SoC;transaction;verification