关键词: 同时多线程 超长指令字 cache冲突 取指 无效地址

Abstract:

In a simuhaneous multithreaded processor, improving the throughput of the instruction fetch unit usually means that there is more drastic cache compet  ition between threads, but this competition limits the throughput reversely. Based on the characteristics of the current VLIW architectures,this paper presents an instruction fetch scheme that improves the throughput of the fetch unit and the whole processor. By canceling the invalid addresses in the in struction fetching pipeline, it decreases those conflicts of program caches caused by invalid instruction fetch. As the experimental results show, this scheme can improve the throughput of the instruction unit and the performance of the whole processor by 12～23% relatively,while the program cache＇s mi  iss rate increases appreciably, even decreases sometimes. It also reduces the program cache＇s accesses by 10%～25%, so the power consumption of the who  ole processor is decreased.

Key words: （SMT, VLIW, cache conflict, instruction fetch, invalid address）