关键词: 超长指令字 动态调度 确定延迟

Abstract:

The VLIW （Very Long Instruction Word） architecture is one of the most important means to explore ILP （Instruction Level Parallelism）. It has the a dvantages of regular structure and low hardware complexity. But the exploration of ILP is limited by only the compiler＇s instruction scheduling. A dyna amic scheduling mechanism for VLIW processors which is based on the deterministic latency of instructions is proposed in this paper. It schedules instructions according to the real-time information, and maintains the data dependency using the deterministic latency scheme. The results of experiments on F  PGA indicate that the mechanism features linear hardware complexity.

Key words: VLIW;dynamic scheduling;deterministic latency