关键词: FPGA FFT蝶形单元 3输入浮点加法器

Abstract:

In this paper, we design and implement a 32-bit IEEE 754 single precision floating-point FFT processor. Usually, limited by the long pipeline latency of floating-point operations and the number of the RAM ports on the FPGA chips the throughput of the traditional FFT processors can only reach approxima   tely one result per cycle. Through making some improvements on the design of the butterfly unit architecture and reorganizing the RAM access, almost a throughput of 2 complex results per cycle can be obtained and twice performance over the traditional FFT processors can be achieved. As to a 1 024-point  FFT transform, it can be finished in （512＋10） ＊ 10=5 220 cycles.

Key words: FPGA, FFT, butterfly unit, 3-input floating-point adder