关键词: 数字信号处理器 高速缓存 失效 超长指令字 双簇 流水线

Abstract:

In digital signal processors, the data cache is a key element. It is important for the designer to consider how to reduce the overhead caused by cache  miss. Especially in the dual cluster VLIW DSP that we have developed, the cache miss will stall all 8 pipelines in the kernel. So an optimization desig   n of the data cache will get a great performance improvement. In this paper, we present four techniques for optimizing the data cache： early read reque   est, request word first, merging two parallel read misses, and background processing snooping. The simulation results show that these methods can improv  e the processor ＇s performance by 8. 36 %.

Key words: digital signal processor, cache, miss, VLIW, dual cluster, pipeline