面向片上网络容错偏转路由器设计与优化

J4 ›› 2012, Vol. 34 ›› Issue (2): 56-61.

面向片上网络容错偏转路由器设计与优化

冯超超，张民选，蒋江，李晋文

（并行与分布处理国防科技重点实验室，湖南长沙 410073）

收稿日期:2010-12-21 修回日期:2011-04-09 出版日期:2012-02-25 发布日期:2012-02-25

Design and Optimization of a FaultTolerant Deflection Router for NetworksonChip

FENG Chaochao,ZHANG Minxuan,JIANG Jiang,LI Jinwen

（National Laboratory for Parallel and Distributed Processing，Changsha 410073,China）

Received:2010-12-21 Revised:2011-04-09 Online:2012-02-25 Published:2012-02-25

摘要/Abstract

摘要：

随着集成电路工艺进入纳米时代，可靠性已成为片上网络设计的一个关键因素。本文设计实现了一种基于增强学习的片上网络容错偏转路由器，该路由器在发送包的同时采用增强学习的方法对路由表进行重配置以实现容错路由。为了提高性能，我们对路由器进行了流水线优化设计，采用2级流水线实现。在TSMC 65nm工艺下综合结果表明，2级流水线路由器频率提升了近一倍达到750MHz，而面积开销仅增加了22%。在合成通信模式下的模拟结果表明，2级流水线容错偏转路由器的平均网络延迟优于无流水线路由器。

关键词: 片上网络；容错；偏转路由；性能优化

Abstract:

Reliability has become a key issue of NetworksonChip (NoC) as the technology scales down to the nanoscale domain. In this paper, we design and implement a faulttolerant deflection router based on reinforcement learning for NoC. The router reconfigures the routing table through a reinforcement learning method during packet transmission to achieve faulttolerance. An optimized router with 2 pipeline stages is also implemented to improve the performance of the router. The synthesized results under the TSMC 65〖WTBX〗nm〖WTBZ〗 technology show that the router with 2 pipeline stages can achieve the frequency of 750MHz, which is almost 1x more than that of the original router, while the area only increases by 22%. The simulation results under the synthetic workloads demonstrate that the average network latency of the router with 2 pipeline stages is less than that of the router with no pipeline.

Key words: networksonchip;faulttolerant;deflection routing;performance optimization

冯超超，张民选，蒋江，李晋文. 面向片上网络容错偏转路由器设计与优化[J]. J4, 2012, 34(2): 56-61.

FENG Chaochao,ZHANG Minxuan,JIANG Jiang,LI Jinwen. Design and Optimization of a FaultTolerant Deflection Router for NetworksonChip[J]. J4, 2012, 34(2): 56-61.