占空比优化的1.25GHz CMOS锁相环

J4 ›› 2012, Vol. 34 ›› Issue (2): 62-66.

占空比优化的1.25GHz CMOS锁相环

马卓,郭阳,谢伦国

（国防科学技术大学计算机学院,湖南长沙 410073）

收稿日期:2009-12-21 修回日期:2010-03-25 出版日期:2012-02-25 发布日期:2012-02-25

1.25GHz CMOS PLL With the Duty Optimizing Technique

MA Zhuo,GUO Yang,XIE Lunguo

（School of Computer Science,National University of Defense Technology,Changsha 410073,China）

Received:2009-12-21 Revised:2010-03-25 Online:2012-02-25 Published:2012-02-25

摘要/Abstract

摘要：

半速率高速串行接口同时使用时钟的正/负边沿作为发送数据的定时基准，数据码元的定时长度直接由时钟的占空比决定，因此锁相环的输出时钟的占空比显得尤为重要。本文基于0.13μm CMOS工艺设计实现了一款1.25GHz的高频锁相环。该锁相环基于环形振荡器结构，使用互补相位调节技术实现输出时钟的占空比平衡。流片测试结果表明，该锁相环能够稳定输出1.25GHz的高频时钟，实测输出时钟的占空比能够稳定在49.86%～52.89%的范围内，平均占空比为51.21%。

关键词: 半速率；高速串行接口；锁相环；占空比平衡；互补相位调节

Abstract:

In highspeed SerDes with the half rate structure, the duty of the clock is seriously important, which is the decisive factor for unit intervals. In this article, a 1.25GHz ring oscillator PLL is established on the 0.13μm CMOS process, in which a duty balance circuit is integrated. The result of testing shows the stable output clock is 1.25GHz, and the duty is within the range of 49.86～51.21%, and the mean duty is 51.21%.

Key words: halfrate;SerDes;PLL;duty balance;coupling phase adjustment

马卓,郭阳,谢伦国. 占空比优化的1.25GHz CMOS锁相环[J]. J4, 2012, 34(2): 62-66.

MA Zhuo,GUO Yang,XIE Lunguo. 1.25GHz CMOS PLL With the Duty Optimizing Technique[J]. J4, 2012, 34(2): 62-66.