一种低成本128位高精度浮点SIMD乘加单元的设计与实现

J4 ›› 2012, Vol. 34 ›› Issue (9): 71-76.

一种低成本128位高精度浮点SIMD乘加单元的设计与实现

黄立波，王志英，沈立，马胜

（国防科学技术大学计算机学院，湖南长沙 410073）

收稿日期:2010-12-07 修回日期:2010-12-29 出版日期:2012-09-25 发布日期:2012-09-25
基金资助:
国家自然科学基金资助项目（60803041,60773024,61025009）；国家973计划资助项目（2007CB310901）

Design and Implementation of a LowCost 128bit QuadruplePrecision FloatingPoint SIMD Fused MultiplyAdd Unit

HUANG Libo,WANG Zhiying,SHEN Li,MA Sheng

（School of Computer Science,National University of Defense Technology,Changsha 410073,China）

Received:2010-12-07 Revised:2010-12-29 Online:2012-09-25 Published:2012-09-25

摘要/Abstract

摘要：

SIMD单元集成已经成为提高处理器性能的重要途径之一。虽然定点SIMD单元的硬件复用低成本设计技术已经较为成熟，但是，大部分浮点SIMD单元的硬件设计还停留在简单的硬件复制方法上。本文针对日益增长的128位高精度浮点操作的计算需求，提出了其相应的SIMD低成本硬件结构方案。综合实验结果表明，所提出的SIMD浮点乘加单元比传统128位高精度浮点乘加单元具有更加优化的性能与面积参数。

关键词: 浮点乘加；单指令多数据；四精度

Abstract:

Incorporating the SIMD unit has become one of the important ways to improve the performance of processors.The reused lowcost hardware design method for the fixedpoint SIMD unit is mature,but it is not the case for the floatingpoint SIMD unit,which still remains the simple replication design method. To address the increasing computation demand for 128-bit quadrupleprecision floatingpoint operations,this paper proposes the hardware design of the lowcost 128bit quadrupleprecision floatingpoint SIMD fused multiplyadd (FMA) unit.The experimental results show that the structure of the proposed FMA unit can be more optimized in performance and cost parameters in comparison to the traditional 128bit quadrupleprecision floatingpoint SIMD multipleadd unit.

Key words: floatingpoint fused multiplyadd；SIMD；quadruple precision

黄立波，王志英，沈立，马胜. 一种低成本128位高精度浮点SIMD乘加单元的设计与实现[J]. J4, 2012, 34(9): 71-76.

HUANG Libo,WANG Zhiying,SHEN Li,MA Sheng. Design and Implementation of a LowCost 128bit QuadruplePrecision FloatingPoint SIMD Fused MultiplyAdd Unit[J]. J4, 2012, 34(9): 71-76.

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