• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2013, Vol. 35 ›› Issue (5): 1-8.

• 论文 •    下一篇

一种分布控制双时钟FIFO的设计与实现

杨剑新,胡向东,李媛   

  1. (国家高性能集成电路(上海)设计中心,上海 201204,China)
  • 收稿日期:2012-01-19 修回日期:2012-09-06 出版日期:2013-05-25 发布日期:2013-05-25
  • 基金资助:

    国家“核高基”重大专项课题资助项目(2009ZX01028002001)

Design and implementation of a distributed-controlled dual-clock FIFO

YANG Jianxin,HU Xiangdong,LI Yuan   

  1. (National HighPerformance IC Design Center,Shanghai 201204,China)
  • Received:2012-01-19 Revised:2012-09-06 Online:2013-05-25 Published:2013-05-25

摘要:

双时钟FIFO是一种常用的跨时钟域数据交接电路。随着SoC芯片内部时钟域种类的增加,传统方式实现的双时钟FIFO会增加时钟网络设计的复杂度,这已经成为影响芯片规模扩大和频率提升的因素之一。提出了一种分布控制双时钟FIFO结构,运用源同步数据传输技术,避免了将发送方时钟树分布到接收方而增加时钟网络设计的复杂度。详细介绍了该结构的一种实现方法,并针对性能和可实现性,简要介绍了该设计可进一步采取的优化措施。

关键词: 双时钟FIFO, 分布控制, 源同步数据传输, 同步器, Gray码

Abstract:

Dual-clock FirstInput First-Out (FIFO) structure is very useful for transferring data between modules operating in different clock domains. As more and more independent clock domains are integrated onto a SystemonaChip (SoC), the traditional dualclock FIFO structure increases the design complexity of clock networks, thus blocking the increase of the chip size and the frequency. The paper proposed a distributedcontrolled dualclock FIFO structure. The proposal uses the technology of sourcesynchronous data transfer so as to avoid the design complexity of clock networks, which is induced by distributing the sender's clock into the receiver's clock domain. The paper implemented this design and further introduced its optimization according to the performance and the realizability.

Key words: dualclock FIFO; distributed controlled; source synchronous data transfer; synchronizer; Gray code