萤火虫2：一种多态并行机的硬件体系结构

J4 ›› 2014, Vol. 36 ›› Issue (02): 191-200.

• 论文 • 下一篇

萤火虫2：一种多态并行机的硬件体系结构

李涛1,杨婷1,易学渊1,蒲林1,钱博文1,黄光新2,黄虎才2,韩俊刚2

(1.西安邮电大学电子工程学院,陕西西安 710061;2.西安邮电大学计算机学院,陕西西安 710061)

收稿日期:2013-08-11 修回日期:2013-10-20 出版日期:2014-02-25 发布日期:2014-02-25
基金资助:
国家自然科学基金重大项目(61136002)；西安邮电大学陕西省2012重点学科建设西邮计算机体系结构项目

Architecture of a polymorphous parallel computer

LI Tao1,YANG Ting1,YI Xueyuan1,PU Lin1,QIAN Bowen1,
HUANG Guangxin2,HUANG Hucai2,HAN Jungang2

(1.School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710061;
2.School of Computer Science,Xi’an University of Posts and Telecommunications,Xi’an 710061,China)

Received:2013-08-11 Revised:2013-10-20 Online:2014-02-25 Published:2014-02-25

摘要/Abstract

摘要：

提出了一种新型的多态高效并行阵列机结构——萤火虫2号阵列机。该结构的处理单元可以在SIMD和MIMD两种模式下运行，兼有异步执行机制，还可以实现分布式指令级并行处理。采用了硬件的多线程管理器和高效通信机制，这些机制使得此种阵列机能够实现效率很高的线程级并行运算、数据级并行运算和分布式指令级并行运算。尤其值得指出的是，此种阵列机的流处理性能堪与专用集成电路匹敌。该结构还能有效实现静态与动态数据流计算，可以高效实现图形、图像和数字信号处理任务。

关键词: 阵列机；多态处理器；计算机图形；图像处理；信号处理；数据级并行；线程级并行；指令级并行

Abstract:

A novel and efficient polymorphous array architecture, the Firefly2, is proposed. Its Processing Element (PE) can run in both SIMD and MIMD modes. The PE supports asynchronous interthread communication and efficient parallel execution of distributed instructions. A PE contains a multithread manager to realize onestep context switching and a router for fast data communication. This architecture is highly efficient in realizing parallel computation at thread level, data level, and instruction level. In particular, the performance of this architecture is comparable with ASIC when used for stream processing. This architecture is capable of implementing highperformance, classical static and dynamic dataflow computation. The architecture is designed for computer graphics, image processing and digital signal processing applications.

Key words: array computer;polymorphous processor;computer graphics;image processing;digital signal processing;data level parallelism;thread level parallelism;instruction level parallelism

李涛1,杨婷1,易学渊1,蒲林1,钱博文1,黄光新2,黄虎才2,韩俊刚2. 萤火虫2：一种多态并行机的硬件体系结构[J]. J4, 2014, 36(02): 191-200.

LI Tao1,YANG Ting1,YI Xueyuan1,PU Lin1,QIAN Bowen1,HUANG Guangxin2. Architecture of a polymorphous parallel computer [J]. J4, 2014, 36(02): 191-200.

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萤火虫2：一种多态并行机的硬件体系结构

Architecture of a polymorphous parallel computer

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