一款低噪声八相位锁相环设计

J4 ›› 2016, Vol. 38 ›› Issue (01): 28-32.

一款低噪声八相位锁相环设计

宋意良,袁珩洲,刘尧,梁斌,郭阳

（国防科学技术大学计算机学院,湖南长沙 410073）

收稿日期:2015-08-11 修回日期:2015-11-15 出版日期:2016-01-25 发布日期:2016-01-25
基金资助:
重点建设经费——研究生创新计划（4345133235）

A low noise eight phase locked loop design

SONG Yiliang,YUAN Hengzhou,LIU Yao,LIANG Bin,GUO Yang

（College of Computer,National University of Defense Technology,Changsha 410073,China）

Received:2015-08-11 Revised:2015-11-15 Online:2016-01-25 Published:2016-01-25

摘要/Abstract

摘要：

基于宽频率范围数字系统的需求，在0.13 μm工艺下设计了一款宽输出范围、低抖动八相位锁相环。首先通过数学建模优化环路带宽，在系统级减小环路噪声；在振荡器中引入了前馈传输管单元以提高振荡频率并降低振荡器相位噪声；最后利用具有伪静态结构的D触发器来降低鉴相器和分频器的功耗并提高其抗噪声能力。仿真结果表明，VCO输出频率在1.2 GHz时相位噪声为-95 dBc/Hz@1 MHz,FOM功耗为4.5 PJ@2 GHz。

关键词: 电荷泵锁相环, 环路带宽, 低相位噪声, 多相位, 宽输出范围

Abstract:

To meet the needs of a wide frequency range of digital systems, we design a wide output range, low phase jitter eightphase lock loop in the 0.13μm process. We first optimize the loop bandwidth through mathematical modeling to reduce the loop noise at the system level. A feedforward transfer tube unit is introduced to increase the oscillation frequency and to reduce the oscillator's phase noise. Finally, we leverage the D flipflop, which has a pseudostatic structure, to reduce the power consumption of phase detectors and dividers, and maximize the noise immunity. Simulation results show that the phase noise is -95 dBc/Hz@1 MHz,FOM power is 4.5 PJ@2 GHz when the VCO output frequency is 1.2 GHz.

Key words: CPPLL;loop bandwidth;low phase noise;multiphase;wide output range

宋意良,袁珩洲,刘尧,梁斌,郭阳. 一款低噪声八相位锁相环设计[J]. J4, 2016, 38(01): 28-32.

SONG Yiliang,YUAN Hengzhou,LIU Yao,LIANG Bin,GUO Yang. A low noise eight phase locked loop design [J]. J4, 2016, 38(01): 28-32.

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