• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学 ›› 2022, Vol. 44 ›› Issue (02): 199-206.

• 高性能计算 • 上一篇    下一篇

硅转接层高带宽存储互连通道信号完整性设计及仿真

李川,郑浩,王彦辉   

  1. (江南计算技术研究所,江苏 无锡 214083)

  • 收稿日期:2021-10-09 修回日期:2021-12-11 接受日期:2022-02-25 出版日期:2022-02-25 发布日期:2022-02-17

Design and analysis of high-bandwidth memory channel on silicon interposer

LI Chuan,ZHENG Hao,WANG Yan-hui   

  1. (Jiangnan Institute of Computing Technology,Wuxi 214083,China)
  • Received:2021-10-09 Revised:2021-12-11 Accepted:2022-02-25 Online:2022-02-25 Published:2022-02-17

摘要: HBM存储器由于超高的存储带宽在大数据、智能计算等领域具有广阔的应用前景。支持超细线宽的硅转接板是实现存储器与芯片间HBM信号互连的主要载体,从HBM1.0到HBM2E,信号速率达到3.2 Gbps,信号完整性问题不容忽视。从HBM颗粒管脚阵列结构出发,分析信号布线和线宽间距极值。建立2层信号线传输模型,提炼频域阻抗分析方法和总串扰计算方法,从频域角度分析结构参数对电性能传输参数的影响,并从时域进行验证。结果显示:HBM信号线宽间距和应小于6.8 μm;在应用频点范围内,远硅层信号线阻抗比近硅层信号线阻抗高6~8 Ω,3 μm线宽的阻抗值更接近于50 Ω;线宽和线长是插入损耗敏感参数,间距和布线层对损耗影响较小。针对低频区的固有损耗,线宽影响占主导,针对高频区线损耗,线长影响较大。间距是串扰敏感因素,但受空间限制,间距优化有限,引入地屏蔽线是有效的解决办法。

关键词: HBM;硅转接层;信号完整性;阻抗;插入损耗;总串扰;眼图 

Abstract: High-Bandwidth Memory (HBM) memory has broad application prospects in big data, intelligent computing and other fields due to its ultra-high storage bandwidth. The silicon interposer that supports ultra-fine-pitch technology is the main carrier to realize the HBM signal interconnection between the memory and the chip. From HBM1.0 to HBM2E, the signal rate reaches 3.2 Gbps, and the signal integrity problem cannot be ignored. Starting from HBM ball map, the signal line distribution, line-width constraint and line-gap constraint are analyzed. A two-layer signal line transmission model is established. The frequency domain impedance analysis method and the total crosstalk calculation method are constructed. The influence of structural parameters on the transmission parameters of electrical properties is analyzed from the frequency domain and verified in the time domain. The result shows that the sum of the HBM signal line width and gap should be less than 6.8 μm. In the application frequency range, the impedance of the signal line at the far silicon layer is 6~8 Ω higher than the impedance of the signal line near the silicon layer, and the impedance value of the 3 μm line width is closer to 50 Ω. Line width and line length are sensitive parameters for insertion loss, and gap and wiring layers have little effect on loss. For the inherent loss in the low frequency area, the line width influence is dominant. For the line loss in the high frequency area, the line length has a greater influence. Line gap is a sensitive factor for crosstalk. However, due to space constraints, spacing optimization is limited. The introduction of ground shielding wire is an effective solution. 

Key words: High-Bandwidth Memory, silicon interposer, signal integrity, impedance, insertion loss, crosstalk, eye diagram