一种HEVC帧内预测算法的动态自重构实现方法

计算机工程与科学 ›› 2022, Vol. 44 ›› Issue (12): 2120-2127.

一种HEVC帧内预测算法的动态自重构实现方法

崔馨月1，蒋林2，杨坤2，惠超1，胡传瞻3，赵静1

(1.西安邮电大学电子工程学院,陕西西安 710121;2.西安科技大学集成电路实验室,陕西西安 710054;
3.西安邮电大学计算机学院,陕西西安 710121)

收稿日期:2021-06-07 修回日期:2021-09-23 接受日期:2022-12-25 出版日期:2022-12-25 发布日期:2022-12-25
基金资助:
国家自然科学基金(61834005，61802304,61772417,61602377)

A dynamic self-reconfigurable implementation method of HEVC intra prediction algorithm

CUI Xin-yue1,JIANG Lin2,YANG Kun2,HUI Chao1,HU Chuan-zhan3,ZHAO Jing1#br#

(1.School of Electronic Engineering,Xi’an University of Posts and Telecommunications,Xi’an 710121;
2.Laboratory of Integrated Circuit,Xi’an University of Science and Technology,Xi’an 710054;
3.School of Computer,Xi’an University of Posts and Telecommunications,Xi’an 710121,China)

Received:2021-06-07 Revised:2021-09-23 Accepted:2022-12-25 Online:2022-12-25 Published:2022-12-25

摘要/Abstract

摘要： 高效视频编码HEVC中帧内预测算法在专用硬件上的实现无法满足在高清和移动视频等多种应用场景间灵活切换的需求，导致编码性能差，硬件资源利用率不高。针对这一问题，提出一种新的帧内预测算法在可重构阵列处理器上的实现方法。该方法基于状态监测机制监测处理单元的执行状态，监测到空闲状态的处理单元则下发新的执行任务，根据处理单元的执行状态实现不同映射方案间的灵活切换，达到算法执行过程的动态自重构。实验结果表明，与帧内预测算法在专用处理器上的实现相比，本文方法在提高灵活性的同时，硬件资源使用减少了33.6%，算法执行的时钟周期数减少了16.2%。不同测试序列经过整个I帧环路测试的结果，与HM16.7官方软件的测试结果相比，平均图像质量有所提高。

关键词: 动态自重构, 阵列处理器, 状态监测器, 高效视频编码, 帧内预测

Abstract: The implementation of intra-frame prediction algorithm in High Efficiency Video Coding (HEVC) on dedicated hardware cannot meet the requirements of flexible switching between various application scenarios such as HD and mobile video, resulting in poor coding performance and low utilization of hardware resources. To solve this problem, a new implementation method of intra-frame prediction algorithm on the reconfigurable array processor is proposed. The method is based on the state monitoring mechanism. When the idle processing unit is detected, a new execution task is delivered, and the flexible switching between different mapping schemes is realized according to the execution state of the processing unit, so as to achieve the dynamic self-reconstruction of the algorithm execution process. The experimental results show that, compared with the implementation of the intra prediction algorithm on the dedicated processor, the hardware resources are reduced by 33.6% and the number of clock cycles is reduced by 16.2%. Compared with the test results of HM16.7 official software, the average image quality is improved.

Key words: dynamic self-reconfiguration, array processor, state monitor, high efficiency video coding (HEVC), intra-frame prediction ,

崔馨月, 蒋林, 杨坤, 惠超, 胡传瞻, 赵静. 一种HEVC帧内预测算法的动态自重构实现方法[J]. 计算机工程与科学, 2022, 44(12): 2120-2127.

CUI Xin-yue, JIANG Lin, YANG Kun, HUI Chao, HU Chuan-zhan, ZHAO Jing. A dynamic self-reconfigurable implementation method of HEVC intra prediction algorithm[J]. Computer Engineering & Science, 2022, 44(12): 2120-2127.

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