MVSim：面向VLIW多核向量处理器的快速、可扩展和精确的体系结构模拟器

计算机工程与科学 ›› 2024, Vol. 46 ›› Issue (02): 191-199.

MVSim：面向VLIW多核向量处理器的快速、可扩展和精确的体系结构模拟器

刘仲1,2,李程1,2，田希1,2，刘胜1,2,邓让钰1,2，钱程东3

（1.国防科技大学计算机学院，湖南长沙 410073;2.先进微处理器芯片与系统重点实验室，湖南长沙 410073；
3.天津先进CPU企业重点实验室，天津 300000）

收稿日期:2023-09-01 修回日期:2023-10-27 接受日期:2024-02-25 出版日期:2024-02-25 发布日期:2024-02-24
基金资助:
国防科技大学自主基金(23-ZZCX-JDZ-11)；PDL重点实验室基金(2021-KJWPDL-11)

MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors

LIU Zhong1,2,LI Cheng1,2,TIAN Xi1,2,LIU Sheng1,2,DENG Rang-yu1,2,QIAN Cheng-dong3

（1.College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;
2.Key Laboratory of Advanced Microprocessor Chips and Systems,Changsha 410073;
3.Tianjin Advanced CPU Enterprise Key Laboratory,Tianjin 300000,China）

Received:2023-09-01 Revised:2023-10-27 Accepted:2024-02-25 Online:2024-02-25 Published:2024-02-24

摘要/Abstract

摘要： 设计了一个面向VLIW多核向量处理器的快速、可扩展、精确的体系结构模拟器MVSim。设计了可扩展的VLIW多核向量处理器模型、多级存储体系结构模型和多核性能模型；实现了指令集架构的节拍精准模拟，Cache、DMA和多核同步部件的高效功能模拟，采用多线程技术实现了多核处理器的高效和可扩展模拟。实验结果表明，MVSim能够准确模拟多核处理器的目标程序执行，模拟结果完全正确，具有良好的可扩展性。MVSim的平均模拟速度分别是RTL模拟和CCS的227倍和5倍，平均性能误差约为2.9%。

关键词: 体系结构模拟器, VLIW, 多核向量处理器模型, 性能模型, 节拍精准模拟器

Abstract: This paper designs a fast, scalable and accurate architecture simulator (MVSim) for VLIW multi-core vector processors. The scalable VLIW multi-core vector processor model, multi-level storage architecture model and multi-core performance model are designed in MVSim. It implements cycle-accurate simulation of instruction set architectures, efficient functional simulation of Cache, DMA and multi-core synchronization, and uses multi-threading to achieve efficient and scalable simulation of multi-core processors. The experimental results show that MVSim can accurately simulate the program execution of the target multi-core processor, the simulation results are completely correct, and it has good scalability. The average simulation speed of MVSim is 227 times and 5 times faster than RTL simulator and CCS, respectively, and the average performance error is about 2.9%.

Key words: architecture simulator, VLIW, multi-core vector processor model, performance model, cycle-accurate simulator

刘仲, 李程, 田希, 刘胜, 邓让钰, 钱程东. MVSim：面向VLIW多核向量处理器的快速、可扩展和精确的体系结构模拟器[J]. 计算机工程与科学, 2024, 46(02): 191-199.

LIU Zhong, LI Cheng, TIAN Xi, LIU Sheng, DENG Rang-yu, QIAN Cheng-dong. MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors[J]. Computer Engineering & Science, 2024, 46(02): 191-199.

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