面向芯粒间互连的低功耗发射机驱动设计

计算机工程与科学 ›› 2024, Vol. 46 ›› Issue (04): 599-605.

面向芯粒间互连的低功耗发射机驱动设计

任博琳，肖立权，齐星云，张庚，王强，罗章，庞征斌，徐佳庆

（国防科技大学计算机学院，湖南长沙 410073）

收稿日期:2023-09-12 修回日期:2023-11-19 接受日期:2024-04-25 出版日期:2024-04-25 发布日期:2024-04-17
基金资助:
国家重点研发计划（2022YFB4401504）

A low-power transmitter driver for die to die

REN Bo-lin,XIAO Li-quan,QI Xing-yun,ZHANG Geng,WANG Qiang,LUO Zhang,PANG Zheng-bin,XU Jia-qing

(College of Computer Science and Technology，National University of Defense Technology,Changsha 410073,China)

Received:2023-09-12 Revised:2023-11-19 Accepted:2024-04-25 Online:2024-04-25 Published:2024-04-17

摘要/Abstract

摘要： 面向UCIe协议提出的芯粒间互连标准，设计与实验了一种面向芯粒（Chiplet）间互连的低功耗发射机驱动。该驱动电路采用了SST电压模驱动器，功耗仅为CML电流模驱动器结构的1/4。此外，该驱动电路基于可调前馈均衡技术，针对不同的信道衰减调整均衡强度，采用去加重均衡的方式提高发射信号质量，最终降低码间干扰。本文设计采用CMOS 28 nm工艺设计，前端仿真结果表明，在0.9 V电压供电时，最大均衡强度为-3.7 dB，当32 Gbps的NRZ信号通过21 mm的信道时（16 GHz奈奎斯特频率处衰减为-2.37 dB），选择合适均衡强度后，输出波形眼图眼高为253 mV（71.8%），眼宽为27 ps（87%），仿真功耗仅为4.0 mW。

关键词: 芯粒, 前馈均衡器, SST驱动器, 高速接口电路, 发射机

Abstract: A low-power transmitter driver for chiplet interconnection was designed and experimentally implemented based on the inter-chip interconnection standard proposed by the UCIe protocol. The driver circuit adopts a source series terminated (SST) driver, whose power consumption is only 1/4 that of the current mode logic (CML) structure. In addition, based on adjustable feedforward equalization technology, the driver circuit adjusts the equalization strength for different channel attenuations. By de-emphasizing equalization, it enhances the quality of the transmitted signal, ultimately reducing inter-symbol interference. This circuit was designed under CMOS 28 nm process. The front-end simulation results show that the maximum equalization intensity is -3.7 dB when the 0.9 V voltage is supplied. When the 32 Gbps NRZ signal passes through the 21 mm channel (the attenuation at the 16 GHz Nyquist frequency is -2.37 dB), after adjusting the appropriate equalization intensity, the eye height of the output waveform eye diagram is 253 mV (71.8%), the eye width is 27 ps (87%), and the simulation power consumption is only 4.0 mW.

Key words: Chiplet, feedforward equalizer(FFE), source series terminated(SST) driver, serDes, transmitter

任博琳, 肖立权, 齐星云, 张庚, 王强, 罗章, 庞征斌, 徐佳庆. 面向芯粒间互连的低功耗发射机驱动设计[J]. 计算机工程与科学, 2024, 46(04): 599-605.

REN Bo-lin, XIAO Li-quan, QI Xing-yun, ZHANG Geng, WANG Qiang, LUO Zhang, PANG Zheng-bin, XU Jia-qing. A low-power transmitter driver for die to die[J]. Computer Engineering & Science, 2024, 46(04): 599-605.

参考文献［13］

［1］	蒋剑飞,王琴,贺光辉,等.Chiplet技术研究与展望［J］.微电子学与计算机,2022,39(1):1-6.
	Jiang Jian-fei,Wang Qin,He Guang-hui, et al.Research and prospects of Chiplet technology［J］.Microelectronics & Computer,2022,39(1):1-6.
［2］	陈桂林,王观武,胡健，等.Chiplet封装结构与通信结构综述［J］.计算机研究与发展,2022,59(1):22-30.
	Chen Gui-lin,Wang Guan-wu,Hu Jian,et al.Survey on Chiplet packaging structure and communication structure［J］.Journal of Computer Research and Development,2022,59(1):22-30.
［3］	李应选.Chiplet的现状和需要解决的问题［J］.微电子学与计算机,2022,39(5):1-9.
	Li Ying-xuan.The state-of-the-art of Chiplet and problems need be solved［J］.Microelectronics & Computer,2022,39(5):1-9.
［4］	Debendra D S,Gerald P,Qian Z,et al.Universal chiplet interconnect express (UCIe):An open industry standard for innovations with Chiplets at package level［J］.IEEE Transactions on Components,Packaging and Manufacturing Technology,2022,12(9):1423-1431.
［5］	陈亚楠.6.25 Gbps高速串行多协议数据发送器的设计［D］.北京:中国航天科技集团公司第一研究院,2016.
	Chen Ya-nan.Design of the data transmitter for 6.25 Gbps high-speed serial multi-protocal interface［D］.Beijing:China Aerospace Science and Technology Corporation First Research Institute,2016.
［6］	付玉山,马奎,唐重林,等.一种28 Gbps高速SERDES发射器［J］.微电子学与计算机,2021,38(10):103-108.
	Fu Yu-shan,Ma Kui,Tang Chong-lin,et al.A 28 Gbps high-speed SERDES transmitter［J］.Microelectronics & Computer,2021,38(10):103-108.
［7］	汪晓东.12.5 Gb/s SerDes发送端均衡器设计［D］.南京:东南大学,2021.
	Wang Xiao-dong.Design of a 12.5 Gb/s SerDes transmitter equalizer［D］.Nanjing:Southeast University,2021.
［8］	刘淼.20 Gb/s高速SerDes中CDR与FFE设计［D］.南京:东南大学,2015.
	Liu Miao.Design of CDR and FFE in 20 Gb/s high-speed SerDes［D］.Nanjing:Southeast University,2015.
［9］	Lu Y, Jung K, Hidaka Y. Design and analysis of energy- efficient reconfigurable pre-emphasis voltage-mode transmitters［J］.IEEE Journal of Solid-State Circuits,2013,48(8):1898-1909.
［10］	吕栋斌,吕方旭,王和明,等.面向片上互连的低功耗CNRZ-5 125 Gb/s高速SerDes发射机［J］.空军工程大学学报(自然科学版),2022,23(2):83-89.
	Lü Dong-bin,Lü Fang-xu,Wang He-ming, et al. A low-power and 125 Gb/s high speed SerDes transmitter using CNRZ-5 for on-chip interconnect［J］.Journal of Air Force Engineering University (Natural Science Edition),2022,23(2):83-89.
［11］	刘登宝,王子谦,白雪飞,等.基于SST驱动器的低功耗10 Gbit/s发射机［J］.微电子学,2018,48(3):338-343.
	Liu Deng-bao,Wang Zi-qian,Bai Xue-fei,et al. A low power 10 Gbit/s transmitter based on SST drivers［J］.Microelectronics,2018,48(3):338-343.
［12］	Bai X,Zhao J Z,Zuo S.A 1.89 mW/Gbps SST transmitter with three-tap FFE and impedance calibration［J］.IEICE Electronics Express,2019,16(15):1-5.
［13］	Chan K L,Tan K H,Frans Y,et al. A 32.75-Gb/s voltage-mode transmitter with three-tap FFE in 16-nm CMOS［J］.IEEE Journal of Solid-State Circuits,2017,52(10):2663-2678.