• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学 ›› 2025, Vol. 47 ›› Issue (7): 1152-1161.

• 高性能计算 • 上一篇    下一篇

面向多值逻辑计算的基于CNFET的三元逻辑单元库设计

王蕾1,王洪2,王耀3,朱晓章2,杨智杰1,唐玉华3   

  1. (1.军事科学院国防科技创新研究院,北京 100850;
    2.电子科技大学电子科学与工程学院,四川 成都 611731;
    3.国防科技大学计算机学院,湖南 长沙 410073)

  • 收稿日期:2024-10-18 修回日期:2024-11-01 出版日期:2025-07-25 发布日期:2025-08-25
  • 基金资助:
    国家自然科学基金 (62372461,62032001,62203457);国家科学和工业局国防重点实验室项目(WDZC20235250112)

Design of CNFET-based ternary cell library for multi-valued-logic computing

WANG Lei1,WANG Hong2,WANG Yao3,ZHU Xiaozhang2,YANG Zhijie1,TANG Yuhua3    

  1. (1.Defense Innovation Institute,Academy of Military Sciences,Beijing 100850;
    2.School of Electronic Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731;
    3.College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)
  • Received:2024-10-18 Revised:2024-11-01 Online:2025-07-25 Published:2025-08-25

摘要: 相比二值逻辑,三元逻辑具有更多的逻辑状态,因而基于三元逻辑的电路具有面积小、利用率高、传输效率高和安全性强等优点。利用常见的碳纳米管场效应晶体管(CNFET)搭建了基本三元逻辑门电路,设计了一个逻辑完备的三元逻辑库,提出了减小CNFET的物理信道长度 Lch和源/漏极长度 Ls/Ld的方法来降低转换延迟时间,还以构建的三元逻辑库为基础,设计搭建了一个一位乘法器电路,通过HSPICE仿真,验证了各电路的性能以及降低转换延迟时间的方法的有效性。与之前的三元1-bit乘法器相比,所设计的电路平均转换延迟时间降低了47 ps。在实际电路应用中,所构建的三元逻辑单元库可以用于更高阶电路的电路综合和物理设计,提出的降低三元电路转换延迟时间的方法为未来以高性能微处理器和人工智能芯片为代表的超大规模集成电路提供了思路。

关键词: 碳纳米管场效应管, 三元逻辑, 多值逻辑

Abstract: Compared to binary logic,ternary logic offers more logic states,endowing ternary logic-based circuits with advantages including smaller area,higher utilization,improved transmission efficiency,and enhanced security.This paper implements fundamental ternary logic gates using commonly available carbon nanotube field-effect transistors (CNFETs),establishes a functionally complete ternary logic library,and proposes a method to reduce switching delay by minimizing the CNFETs physical channel lengthand and source/drain length.Based on the developed ternary logic library,a 1-bit multiplier circuit was designed and implemented.HSPICE simulations verified both the circuit performance and the effectiveness of the proposed delay reduction method,demonstrating an average 47 ps reduction in switching delay compared to prior ternary 1-bit multipliers.In the actual circuit application,this paper builds the ternary logic cell library that can be used for higher order circuit synthesis and physical design of the circuit.The method to lower the ternary circuit switching delay time for the future,represented by high-performance chip microprocessor and artificial intelligence to lay a good foundation for very large-scale integration.

Key words: carbon nanotube field-effect transistor(CNFET), tenary logic, multi-valued-logic