关键词: 计算密集型体系 DDR SDRAM控制器 FPGA 仿真

Abstract:

The paper introduces the research trend for the access bottleneck between the data intensive computing architecture and memory. Aiming at the high needs for the data intensive computing architecture＇s access to memory, an integrated DDR SDRAM controller is presented and prototyped in FPGA. The key pooints for the DDR SDRAM controller are a fixed initiation procedure and its dedicated custom system bus. Simulation results and analysis demonstrate thecontroller basically conquers the access bottleneck between the data intensive computing architecture and memory.

Key words: data intensive computing architecture;DDR SDRAM controller;FPGA, simulation