[1]Sodani A. Intel Xeon Phi processor “knights landing” architectural overview[EB/OL].[20151117]. http:∥www.nersc.gov/assets/uploads/KNLISC2015WorkshopKeynote.pdf.
[2]Johnson D R,Johnson M R,Kelm J H,et al. Rigel:A 1,024core singlechip accelerator architecture[J]. IEEE Micro,2011,31(4):3041.
[3]Ahn J,Yoo S,Choi K. Dynamic power management of offchip links for hybrid memory cubes[C]∥Proc of the 51st ACM Annual Design Automation Conference,2014:16.
[4]Park S,Park I. Historybased memory mode prediction for improving memory performance[C]∥Proc of the 2003 IEEE International Symposium on Circuits and Systems,2003:185188.
[5]Miura S, Ayukawa K, Watanabe T. A dynamicSDRAMmodecontrol scheme for lowpower systems with a 32bit RISC CPU[C]∥Proc of the ACM 2001 International Symposium on Low Power Electronics and Design,2001:358363.
[6]Xu Y, Agarwal A S, Davis B T. Prediction in dynamic SDRAM controller policies[C]∥Proc of the 9th International Workshop on Embedded Computer Systems:Architectures,Modeling,and Simulation,2009:128138.
[7]Awasthi M,Nellans D W,Balasubramonian R,et al. Prediction based DRAM rowbuffer management in the manycore era[C]∥Proc of the 11th IEEE International Conference on Parallel Architectures and Compilation Techniques,2011:183184.
[8]Xie M,Tong D,Feng Y,et al. Page policy control with memory partitioning for DRAM performance and power efficiency[C]∥Proc of the 2013 IEEE International Symposium on Low Power Electronics and Design,2013:298303.
[9]Kahn O D,Wilcox J R. Method for dynamically adjusting a memory page closing policy:U.S. Patent 6799241[P]. 2004928.
[10]Sander B T,Madrid P E,Smaus G W. Dynamic idle counter threshold value for use in memory paging policy:U.S. Patent 6976122[P]. 20051213.
[11]Huan D,Li Z,Hu W,et al. Processor directed dynamic page policy [C]∥Proc of the 11th AsiaPacific Computer Systems Architecture Conference,2006:109122.
[12]Binkert N,Beckmann B,Black G,et al. The gem5 simulator[J]. ACM SIGARCH Computer Architecture News,2011,39(2):17. |