As the scale of high performance networks is increasing,the design of highradix router architectures is becoming a hotspot in the field of high performance computing. Using highradix routers, the network can achieve lower transmission latency, lower cost of network construction and lower power consumption, and improve network reliability simultaneously. As the radix of high performance routers increases continuously, simply extending the radix of singlestage crossbar fabric can greatly increase internal connection resources inside the routers, and the cost of switches becomes unbearable.So there is a pressing need to design a new fabric for highradix routers. Over the past decade, the structured designs represented by the YARC and the "network within a network" approach have appeared, and future study focuses on solving all kinds of problems such as buffer and arbitration to design better architectures.We implement a highradix router with a multistage Clos network inside and there are corresponding arbitration modules to schedule requests for each stage. Packet memory buffers are implemented at input and output ports, and the network is bufferless besides these memories. We conduct extensive simulations to evaluate the performance in BookSim simulator, and the results show that the highradix router we design works properly and provides good performance.