[1] |
de Dinechin F,Tisserand A.Multipartite table methods[J].IEEE Transactions on Computers,2005,54(3):319-330.
|
[2] |
Low J Y L, Jong C C. A memory-efficient tables-and- additions method for accurate computation of elementary functions[J].IEEE Transactions on Computers,2013,62(5):858-872.
|
[3] |
de Dinechin F,Istoan M,Sergent G.Fixed-point trigonome- tric functions on FPGAs[J].ACM SIGARCH Computer Architecture News,2013,41(5):83-88.
|
[4] |
Valls J,Kuhlmann M,Parhi K K.Evaluation of CORDIC algorithms for FPGA design[J].Journal of VLSI Signal Processing Systems for Signal,Image and Video Technology,2002,32:207-222.
|
[5] |
Kebbati H S, Blonde J P,Braun F.A new semi-flat architecture for high speed and reduced area CORDIC chip[J].Microelectronics Journal,2006,37(2):181-187.
|
[6] |
Lakshmi B,Dhar A S.VLSI architecture for parallel radix-4 CORDIC[J].Microprocessors and Microsystems,2013,37(1):79-86.
|
[7] |
Strollo A G M,de Caro D,Petra N.Elementary functions hardware implementation using constrained piecewise- polynomial approximations[J].IEEE Transactions on Computers,2011,60(3):418-432.
|
[8] |
Sadeghian M,Stine J,Walters E.Optimized linear,quadratic and cubic interpolators for elementary function hardware implementations[J].Electronics,2016,5(2):17.
|
[9] |
Alimohammad A,Fard S F,Cockburn B F.A unified architecture for the accurate and high-throughput implementation of six key elementary functions[J].IEEE Transactions on Computers,2010,59(4):449-456.
|
[10] |
Chen C.High-order Taylor series approximation for efficient computation of elementary functions[J].IET Computers & Digital Techniques,2015,9(6):328-335.
|
[11] |
Lee D-U,Cheung R,Luk W,et al.Hardware implementation trade-offs of polynomial approximations and interpolations[J].IEEE Transactions on Computers,2008,57(5):686-701.
|
[12] |
Ko H-J,Hsiao S-F,Huang W-L.A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation[C]∥Proc of 2010 IEEE International Symposium on Circuits and Systems,2010:4153-4156.
|
[13] |
Lee D U,Cheung R C C,Luk W,et al.Hierarchical segmentation for hardware function evaluation[J].IEEE Transactions on Very Large Scale Integration Systems,2009,17(1):103-116.
|
[14] |
Iordache C,Matula D W.Analysis of reciprocal and square root reciprocal instructions in the AMD K6-2 implementation of 3DNow![J].Electronic Notes in Theoretical Computer Science,2000,24:34-62.
|
[15] |
Lee D-U,Villasenor J D.A bit-width optimization methodology for polynomial-based function evaluation[J].IEEE Transactions on Computers,2007,56(4):567-571.
|