关键词: 浮点加法器 多输入 FPGA 高效算法

Abstract:

A multiple-input floating-point adder is usually composed of several double-input floating-point adders, and it is inevitable to increase the logic re sources and processing latency, which makes it harder and harder to meet the requirements of high-speed digital signal processing. This article puts for   ward a new floating-point format suitable for implementation on FPGAs and an efficient structure with which the adder can complete calculating ur clock cycles. Test data is presented at the end of this article.

Key words: floating-point adder, multiple input, FPGA, efficient algorithm