[1]Horowitz M, Dally W. How Scaling Will Change Processor Architecture[C]∥Proc of the International SolidState Circuits Conference, 2004:132133.
[2]Borkar S. Thousand Core Chips: A Technology Perspective[C]∥Proc of the Design Automation Conference, 2007:746749.
[3]Marinissen E, Prince B, KeltelSchulz D, et al. Challenges in Embedded Memory Design and Test[C]∥Proc of the Conference of Design, Automation and Test in Europe, 2005:722727.
[4]Macii E, Macii M. Poncino M. Improving the Efficiency of Memory Partitioning by Address Clustering[C]∥Proc of the Conference of Design, Automation and Test in Europe, 2003:1823.
[5]Suh G, Rudolph L, Devadas S. Dynamic Partitioning of Shared Cache Memory[J]. Journal of Supercomputing, 2004, 28(1):726.
[6]Qiu X, Dubois M. Moving Address Translation Closer to Memory in Distributed SharedMemory Multiprocessors[J]. IEEE transactions on Parallel and Distributed Systems, 2005, 16(7):612623.
[7]Pande P, Grecu C, Jones M, et al. Performance Evaluation and Design TradeOffs for NetworkonChip Interconnect Architectures[J]. IEEE Transactions on Computers, 2005, 54(8):10251040.
[8]http://www.gaisler.com.
[9]Jantsch A. The Nostrum NetworkonChip[EB/OL][20100806]. http://www.ict.kth.se/nostrum.
[10]Zhu W, Sreedhar V, Hu Z, et al. Synchronization State Buffer: Supporting Efficient FineGrain Synchronization on ManyCore Architectures[C]∥Proc of the International Symposium on Computer Architecture, 2007:3545. |