[1]Montgomery P L. Modular multiplication without trial division[J]. Mathematics of Computation, 1985, 44(170):519521.
[2]Tenca A F, Ko K. A scalable architecture for Montgomery multiplication[C]∥Proc of Cryptographic Hardware and Embedded Systems, 1999:94108.
[3]Huang M, Gaj K, ElGhazawi T. New hardware architectures for Montgomery modular multiplication algorithm[J]. IEEE Transactions on Computers, 2011, 60(7):923936.
[4]McIvor C, McLoone M, McCanny J V. Highradix systolic modular multiplication on reconfigurable hardware[C]∥Proc of IEEE International Conference on FieldProgrammable Technology, 2005:1318.
[5]Zhou L, Huang M, Smith S C. Highperformance and areaefficient hardware design for radix 2k Montgomery multipliers[C]∥Proc of International Conference on Computer Design, 2011:1.
[6]Batina L, Muurling G. Montgomery in practice:How to do it more efficiently in hardware[C]∥Proc of Topics in Cryptology, the Cryptographer’s Track at the RSA Conference, 2002:4052.
[7]Walter C D. Montgomery’s multiplication technique:How to make it smaller and faster[C]∥Proc of Cryptographic Hardware and Embedded Systems, 1999:8093.
[8]rs S B, Batina L, Preneel B, et al. Hardware implementation of elliptic curve processor over GF(p)[C]∥Proc of IEEE International Conference on ApplicationSpecific Systems, Architectures and Processors, 2003:433443. |