[1]Banerjee K, Souri S J, Saraswat K C, et al. 3D ICs:A novel chip design for improving deepsubmicrometer interconnect performance and systemsonchip integration[J]. Proc of the IEEE, 2001,89(5):602633.
[2]Xu Qiang, Li Jiang, Eklow B, et al. Yield enhancement for 3Dstacked ICs:Recent advances and challenges[C]∥Proc of Asia South Pacic Des Autom Conference, 2012:731737.
[3]Lung Chiaoling,Chien Juihung,Shi Yiyu,et al. TSV faulttolerant mechanisms with application to 3D clock networks[C]∥Proc of SoC Design Conference (ISOCC),2011:127130.
[4]Loi I, Mitra S, Lee T H, et al. A lowoverhead fault tolerance scheme for TSVbased 3D network on chip links[C]∥Proc of the IEEE/ACM International Conference on CAD, 2008:598602.
[5]Hsieh AC, Hwang TT, Chang MT, et al. TSV redundancy:Architecture and design issues in 3D IC[C]∥Proc of IEEE/ACM Design, Automation, and Test in Europe, 2010:166171.
[6]Wang Wei,Dong Fudi,Chen Tian,et al.3DSIC TSV faulttolerant scheme based on multichains[J]. Computer Engineering and Applications, 2012, 48(20):7580. (in Chinese)
[7]Wang Wei, Dong Fudi, Fang Fang, et al. Multichain type configurable faulttolerant scheme in 3DSIC[J]. Electronic Measurement and Instrument,2012, 26(2):126131. (in Chinese)
[8]Noia B. Prebond and postbond test solutions for 3D stacked ICs[Z]. Durham:Duke University, 2012.
[9]Miyakawa.A 3D prototyping chip based on a waferlevel stacking technology[C]∥Prcoc of Design Automation Conference, 2009:416420.
附中文参考文献:
[6]王伟, 董福弟, 陈田,等. 一种多链式结构的3DSIC过硅通孔(TSV)容错方案[J].计算机工程与应用,2012, 48( 20):7580.
[7]王伟, 董福弟, 方芳, 等. 3DSIC中多链式可配置容错结构[J].电子测量与仪器学报,2012, 26(2):126131. |