关键词: 可靠性, 三模冗余, 时序单元, 组合逻辑, 门级网表

Abstract:

Particles in universe may damage spacecrafts to malfunction,and triple modular redundancy (TMR) is an effective faulttolerant technology.However,the existing TMR design is usually specifically customized for a given chip, it can as not be used in general.A novel TMR design scheme is proposed for VLSI gatelevel netlist without considering the function.The scheme contains four design methods, which are global sequential elements TMR,local sequential elements TMR,global combinational logic cells TMR, and local combinational logic cells TMR.According to different libraries,the strategy also optimizes the drive capability.The proposed scheme is verified by a multicore processor netlist.The experimental results show that,the area overhead of global sequential elements TMR is 185% of that of the original netlist,and the area overhead of local sequential elements TMR 1%~80% of that of the original netlist.The scheme can be configured according to designers’requirements.Experimental data show that the delay introduced by the scheme on the critical paths is about 22.15%~22.86%,which is controllable for designers. And the scheme has a relative high reliability.

Key words: reliability;triple modular redundancy (TMR);sequential element;combinational logic;gate-level netlist