关键词: 全数字锁相环, 低抖动, 可综合

Abstract:

The All Digital Phase Locked Loop (ADPLL) features higher design density, flexible configurability, and swift transplant to another technology. The ADPLL can solve some bottleneck problems of analogy PLL, such as the big area of passive devices, sensitivity to noise, long lock time and difficult transplant between technologies. In nanometer technology, the minimmal inverter delay is decreased within ten ps, so the jitter performance of the ADPLL is improved greatly. We introduce a new ADPLL structure used in high performance microprocessors.A Sdomain modeling and a noise analysis are conducted based on the proposed ADPLL. This structure is designed by standard cells.The highest frequency can reach 2.4GHz, and the jitter performance is about 2ps.

Key words: ADPLL;low jitter;synthesisable