Due to limited power consumption, the general-purpose processor stopped pursuing higher frequency more than a decade ago and moved towards integrating more processor cores on a single chip. At the same time, with the increasing density of transistors according to the law of Moore, the number of processor cores integrated on a single chip has been doubled and redoubled, thus multicore and manycore processors have become the mainstream of high-performance processors.  It is an inevitable trend for the future kilo-core general processor to support shared memory programming model. However, the traditional cache coherence directory structure is confronted with the problems of high latency, frequent replacement of directory entries, limited scalability for the hardware cost and power consumption. The sparse directory realizes the tradeoff between the hardware cost of the traditional directory structure and the coherence maintenance efficiency, and is considered as an energy-efficient and scalable structure for many-core processors to maintain cache coherence. We review related research and methods for improving the performance of sparse directory in recent years, analyze their characteristics in terms of area, access delay, power consumption and implementation complexity, and summarize the merits and shortcomings of these directory schemes. It has certain reference significance for designing novel scalable shared memory architectures for future many-core processors.