• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2010, Vol. 32 ›› Issue (7): 76-79.doi: 10.3969/j.issn.1007130X.2010.

• 论文 • 上一篇    下一篇

读写通道基于τ因子内插时钟恢复模型设计与实现

丁红1 ,王庆东2   

  1. (1.上海第二工业大学计算机与信息学院,上海 201209;
    2.华中科技大学计算机科学与技术学院教育部外存储国家专业实验室,湖北 武汉 430074)
  • 收稿日期:2009-06-12 修回日期:2009-09-21 出版日期:2010-06-25 发布日期:2010-06-25
  • 通讯作者: 丁红 E-mail:yvesding@163.com
  • 作者简介:丁红(1975),女,河南平顶山人,讲师,研究方向为网络存储和嵌入式系统;王庆东,博士后,研究方向为海量数据存储。
  • 基金资助:

    国家自然科学基金资助项目(60303031);上海市教育高地建设资助项目

Timing Recovery Model in the Read/Write Channel Based on the τ Factor

DING Hong1,WANG Qingdong2   

  1. (1.School of Computer Science and Information,Shanghai Second Polytechnic University,Shanghai 201209;
    2.National Storage System Laboratory,School of Computer Science and Technology,
    Huazhong University of Science and Technology,Wuhan 430074,China)
  • Received:2009-06-12 Revised:2009-09-21 Online:2010-06-25 Published:2010-06-25
  • Contact: DING Hong E-mail:yvesding@163.com

摘要:

读写通道是介于磁盘读写头与设备控制器之间的电子电路,实现数据写入和可靠的恢复。伺服信号采样时钟是伺服信号检测的重要组成部分,其设计的目标是在提高伺服信号传输速率的同时维持低的误码率,这就对通道的数据采样处理以及时钟恢复电路的设计提出了严格的要求。本文通过对读写通道伺服的分析,对常用的由锁相环构成的伺服时钟恢复电路进行改进,在线性插值时钟恢复的基础上提出了基于τ因子内插时钟恢复模型,并推导出τ因子插值滤波器系数算法,还给出了伺服时钟恢复的硬件及FPGA的设计与实现方案,最后给出了基于线性插值和基于τ因子内插时钟恢复试验。测试结果证明,采用基于τ因子内插滤波器模型可以获得更好的谐波频谱。

关键词: 读写通道, 伺服信号, &tau, 因子, 内插时钟恢复模型

Abstract:

The read/write channel is the electronic circuit between the readwrite head for disks and the device controller,and its main function is to write and recover data reliably.The servo signal sampling clock is an important part of servo signal detection and its design goal is to improve the servo signal transmission rate as well  as maintain the low BER,which makes strict demands on data sampling processing and clock recovery circuit design.This paper offers the servo interpolated timing recovery model based on the τ factor after analysizing the current PLL timing recovery implementation,and adopts a better solution.This paper also deduces the coefficient of interpolator,then studies the realization of the interpolator by hardware and FPGA.Through a comparison test with the linear interpolation scheme,the interpolated model can obtain better harmonic frequency.

Key words: read/write channel;serve signal;&tau, factor;interpolated timing recovery model