[1]Sun Y, Zhang J X, Zhang M X, et al. Reducing vulnerability to soft errors in sub100nm content addressable memory circuits[J]. Journal of Semiconductors, 2010, 31(2):02501310250135.
[2]Mupid A, Mutyam M, Vijaykrishnan N, et al. Variation analysis of CAM cells [C]∥Proc of International Symposium & Exhibits on Quality Electronic Design, 2007:333338.
[3]Li Xiaowei, Hu Yu, Zhang Lei, et al. Fault tolerant design of digital integrated circuits [M]. Beijing:Science Press, 2011.(in Chinese)
[4]Luong D H. Softerror tolerant cache architectures [D]. Tokyo:The University of Tokyo, 2006.
[5]Rabaey J M, Chandrakasan A, Nikolic B. Digital integrated circuits:A design perspective[M]. 2nd Edition. NJ:Prentice Hall,2003.
附中文参考文献:
[3]李晓维, 胡瑜, 张磊,等. 数字集成电路容错设计[M]. 北京:科学出版社, 2011. |