• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2016, Vol. 38 ›› Issue (03): 411-417.

• 论文 • 上一篇    下一篇

多种哈希算法的可重构硬件架构设计

刘恒1,黄凯1,修思文2,李奕均3,严晓浪1   

  1. (1.浙江大学超大规模集成电路研究所,浙江 杭州 310027;
    2.中国计量学院光学与电子科技学院,浙江 杭州 310018;3.杭州朔天科技有限公司,浙江 杭州 310012)
  • 收稿日期:2015-06-10 修回日期:2015-07-22 出版日期:2016-03-25 发布日期:2016-03-25
  • 基金资助:

    浙江省自然科学基金(LY14F020026);中央高校基本科研业务费专项资金(2013QNA5008);国家电网智能电网研究院“新一代智能电网片上系统芯片关键技术研究”(SGRIWD7113014)

A reconfigurable hardware architecture
design for multiple Hash algorithms 

 LIU Heng1,HUANG Kai1,XIU Siwen2,LI Yijun3,YAN Xiaolang1   

  1. (1.Institute of VLSI Design,Zhejiang University,Hangzhou 310027;
    2.College of Optical and Electronic Technology,China Jiliang University,Hangzhou 310018;
    3.Hangzhou SecChip Technology Co.,Ltd.,Hangzhou 310012,China)
  • Received:2015-06-10 Revised:2015-07-22 Online:2016-03-25 Published:2016-03-25

摘要:

针对现有的哈希算法硬件架构仅实现少量几种算法的问题,设计了一种可实现SM3,MD5,SHA1以及SHA2系列共7种哈希算法的可重构IP,以满足同一系统对安全性可选择的需求。通过分析各哈希算法及其运算逻辑的相似性,该设计最大化地重用加法器和寄存器,极大地减少了总的实现面积。此外,该设计灵活可配,可以对内存直接存取。以Altera的Stratix II为FPGA目标器件,其最高频率可达100 MHz,总面积较现有设计减少26.7%以上,且各算法单位面积吞吐率均优于现有设计。

关键词: 哈希算法, SM3, MD5, SHA, 基础运算单元, 可重构, 高性能

Abstract:

Since the existing hardware architecture for Hash algorithms can only implement a few algorithms, we design a reconfigurable IP, which can implement seven Hash algorithms including SM3, MD5, SHA1 and SHA2 family, and it can meet the demand of a system for algorithm diversity. By analyzing all these Hash algorithms and estimating their similarity, the design reuses adders and registers to the maximum extent and therefore greatly reduces the total area. Besides, the design is flexibly configurable and can access the memory directly. The implementation results based on the FPGA of Stratix II of Altera Corporation show that, in comparison with the existing designs, the maximum frequency can achieve 100MHz, the whole area is decreased by more than 26.7% and the throughputperarea for each of the seven algorithms is increased.

Key words: Hash algorithm;SM3;MD5;SHA;basic arithmetic unit;reconfigurable;high performance