The ever-changing network protocol standards and user-customized network services require greater flexibility for switch hardware. Under this background, this paper proposes a basic processing unit of an Ethernet switch chip packet parser, which can define protocol parsing rules by software programming and has the advantages of high performance and high flexibility. Hardware parsing logic and look-up table can be flexibly configured, and the extraction, search, match, action, and other parsing processes of packet header content are defined, so as to support different types of protocol parsing tasks. It is composed of two types of basic structures in series or parallel so that the hardware resources can be tailored according to the need. Based on the reconfigurable basic processing unit, the reconfigurable message parser can be constructed, which supports the parsing of custom protocol and unknown protocol. This paper mainly introduces the structure of the reconfigurable basic processing unit and introduces the implementation method of the parser architecture based on the basic processing unit. The synthesis results under 40nm process show that the maximum working clock frequency of the basic processing unit can reach 240MHz. Based on the basic processing unit, the parser, which supports the parsing of four-layer common Ethernet protocols, can process 240 million packets per second. The total storage resources used in the reconfigurable basic processing unit are 87.98K bit, and the design size is about 1.47 million gates.