基于以太网和PCIe的多核DSP开发平台

计算机工程与科学

基于以太网和PCIe的多核DSP开发平台

张象羽，施慧莉

（中国航空工业集团公司雷华电子技术研究所，江苏无锡 214063）

收稿日期:2019-03-19 修回日期:2019-04-24 出版日期:2019-10-25 发布日期:2019-10-25

A multi-core DSP development

platform based on Ethernet and PCIe

ZHANG Xiang-yu,SHI Hui-li

(AVIC Leihua Electronic Technology Research Institute,Wuxi 214063,China)

Received:2019-03-19 Revised:2019-04-24 Online:2019-10-25 Published:2019-10-25

摘要/Abstract

摘要：

多核数字信号处理器（DSP）在航空、航天等领域的信号处理系统中应用较广泛，在实际工程应用时，由于JTAG接口的性能限制，存在速度慢、不稳定、难操作等问题，导致开发效率低下并严重影响项目进度。建立了一种以千兆以太网和PCIe作为加载和调试接口的多核DSP软硬件开发平台，包括标准化的硬件模块和软件开发环境，具有易重构、易扩展、不再依赖JTAG接口、兼容多个软件操作系统、资源占用低等优点。以多核DSP TMS320C 6678为例，描述了多片DSP组成的信号处理系统开发中的关键技术，包括商用标准（COTS）模块、系统架构、硬件诊断、软件加载、软件调试等。用该平台可以显著降低使用门槛，大幅度提高开发效率。

关键词: 信号处理, 多核DSP, 开发平台, 以太网, PCIe

Abstract:

Multi-core Digital Signal Processor (DSP) is widely used in signal processing systems in aviation, aerospace and other fields. In practical engineering applications, due to the performance limitation of JTAG interface, there are some problems such as slow speed, instability and difficult operation, which lead to low development efficiency and seriously affect the progress of the project. This paper proposes a multi-core DSP software and hardware development platform with Gigabit Ethernet and PCIe as loading and debugging interfaces, including standardized hardware modules and software development environment. It has the advantages of easy reconfiguration, easy expansion, no longer relying on JTAG interface, compatibility with multiple software operating systems, and low resource occupation.Taking the multi-core DSP TMS320C 6678 as an example, this paper describes the key techniques in the development of the signal processing system composed of multi-chip DSPs, including COTS module, system architecture, hardware diagnoising, software loading, software debugging and so on. This platform can significantly reduce the application threshold and greatly improve the development efficiency.

Key words: signal processing, multi-core DSP, development platform, Ethernet, PCIe

张象羽，施慧莉. 基于以太网和PCIe的多核DSP开发平台[J]. 计算机工程与科学.

ZHANG Xiang-yu,SHI Hui-li.

A multi-core DSP development

platform based on Ethernet and PCIe

[J]. Computer Engineering & Science.

[1]	田玉恒,马胜,鲁建壮,杨柳. 一种高效的DMA核间同步传输方法[J]. J4, 20160101, 38(01): 52-56.
[2]	翦杰, 罗章, 赖明澈, 肖立权, 徐炜遐. 基于深度神经网络的高速信道自适应均衡器[J]. 计算机工程与科学, 2022, 44(04): 605-610.
[3]	林楷智, 宗艳艳, 孙珑玲, . AI服务器PCIe拓扑应用研究[J]. 计算机工程与科学, 2022, 44(03): 390-395.
[4]	孙兆鹏, 周宽久. 基于PCIe的高性能FPGA-GPU-CPU异构编程架构[J]. 计算机工程与科学, 2021, 43(04): 641-651.
[5]	赵宇1,2，殷树娟1，李翔宇2. 一种可重构以太网数据包解析器中可重构单元的设计[J]. 计算机工程与科学, 2020, 42(02): 220-228.
[6]	田玉恒,马胜,鲁建壮,杨柳. 一种高效的DMA核间同步传输方法[J]. J4, 2016, 38(01): 52-56.
[7]	檀明. 主从交换式以太网中跨多Switch传输消息实时调度研究[J]. J4, 2015, 37(10): 1862-1868.
[8]	檀明. 主从结构交换式以太网中实时消息调度研究[J]. J4, 2014, 36(12): 2312-2320.
[9]	孙中豪,周兴社,张凯龙. 基于μC/OSII的Modbus/TCP消息的类令牌环实时响应算法[J]. J4, 2014, 36(09): 1662-1667.
[10]	李涛1,杨婷1,易学渊1,蒲林1,钱博文1,黄光新2,黄虎才2,韩俊刚2. 萤火虫2：一种多态并行机的硬件体系结构[J]. J4, 2014, 36(02): 191-200.
[11]	谭志国1,鲁敏1,胡延平2,郭裕兰1,庄钊文1. 基于点云-模型匹配的激光雷达目标识别[J]. J4, 2012, 34(4): 32-36.
[12]	游鸿1,2，于文震1. 基于阵列的盲信号处理研究和应用[J]. J4, 2012, 34(4): 128-132.
[13]	巩微,冯欣. 一种粗糙模糊神经网络模型的研究及应用[J]. J4, 2010, 32(6): 132-134.
[14]	马鹏勇陈书明孙锁林. 双簇结构DSP的数据Cache优化[J]. J4, 2008, 30(9): 119-121.
[15]	柳笛黎福海闫旭. 基于DSP的嵌入式图像监控系统的设计与实现[J]. J4, 2008, 30(2): 39-41.